Abstract: A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.

Abstract: A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).

Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: One embodiment of the present invention is a one transistor DRAM cell having enhanced capacitance and minimized soft error rate by providing an ungrounded cell capacitor plate which is insulated from the substrate. The structure includes a vertical transistor on the sides of a vertical depression or trench in a substrate. In the bottom of the trench, a memory cell capacitor is fabricated. This capacitor includes a conductive polycrystalline silicon post through the middle of the capacitor, thereby increasing the surface area of the capacitor plates. This increases the capacitance of the memory cell capacitor.The ungrounded plate of the memory cell capacitor is fabricated in the trench and is insulated from the substrate. This ungrounded plate is connected to the vertical transistor via a polycrystalline silicone plug. Thus this embodiment of the present invention reduces soft error rate by providing a fully insulated ungrounded memory cell capacitor plate.

Abstract: A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.

Abstract: Preferred embodiments include growth of GaAs on insulator-masked silicon; the GaAs is single crystal over the silicon but polycrystalline over the insulator. A post=growth anneal extends the single crystal region over the insulator for distances of 2-4 .mu.m.

Abstract: A lift-off method for forming regions of a first semiconductor such as GaAs (104) in recesses in a substrate of a second semiconductor such as silicon (102) with the surface of the first semiconductor region (104) coplanar with the surface of the second semiconductor layer (102). Also, interconnected devices in both regions. Preferred embodiment methods include growth by molecular beam epitaxy of a layer of the first semiconductor on a masked and recessed substrate of the second semiconductor followed by photolithographic removal of the grown layer outside of a neighborhood of the recesses and lift-off (by mask etching) of the remainder of the grown layer outside of the recesses.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Abstract: A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.