Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

Abstract: In a FET having a thin-film SOI layer, to prevent a parasitic resistance increase in source/drain regions. To realize an elevated layer to be formed on the source/drain region without using a lithography process and without a fear of a short circuit. Element-isolation insulating films 7, which are taller than a semiconductor layer 3, are formed surrounding the island-shaped semiconductor layer (SOI layer) 3, while gate electrodes 5a, 8a which are taller than the element-isolation insulating films 7 are formed on the semiconductor layer 3. A polycrystalline silicon film 11 is deposited on the whole surface. elevated layers 11a, 11b which are shorter than the element-isolation insulating film 7 are formed on the source/drain regions 3a, 3b by chemical-mechanical polishing and etching back. Silicide layers 13a to 13c are formed on the gate electrode and on the elevated layers. An interlayer insulating film 14 is formed, and a metal electrode 16 is formed.

Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

Abstract: A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

Abstract: In a FET having a thin-film SOI layer, to prevent a parasitic resistance increase in source/drain regions. To realize an upheaved layer to be formed on the source/drain region without using a lithography process and without a fear of a short circuit. Element-isolation insulating films 7, which are taller than a semiconductor layer 3, are formed surrounding the island-shaped semiconductor layer (SOI layer) 3, while gate electrodes 5a, 8a which are taller than the element-isolation insulating films 7 are formed on the semiconductor layer 3. A polycrystalline silicon film 11 is deposited on the whole surface. Upheaved layers 11a, 11b which are shorter than the element-isolation insulating film 7 are formed on the source/drain regions 3a, 3b by chemical-mechanical polishing and etching back. Silicide layers 13a to 13c are formed on the gate electrode and on the upheaved layers. An interlayer insulating film 14 is formed, and a metal electrode 16 is formed.

Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: A field-emission type cold cathode is disclosed, by which the degradation of the withstand voltage between the gate electrode and emitter and discharge destruction are suppressed, and the operating voltage and the distance between the gate electrode and emitter can be reduced. The cold cathode comprises a substrate (on a surface of which an emitter is formed) for functioning as a leading emitter electrode; and a gate electrode, formed via an insulating film on the substrate, having an aperture which surrounds the emitter via a space. The height of a boundary (which faces the space) between the insulating film and the substrate is lower than the height of the surface of the substrate on which the emitter is formed. An insulated trench surrounds the area on which the emitter is formed, where the above boundary is placed between the emitter and the trench, and a part of the insulating film is present between the boundary and the trench.

Abstract: An electric field emission cold cathode which is free of short-circuited damage upon discharge is provided by forming a highly voltage-withstandable control mechanism, which is capable of limiting generation of current upon discharge, with a simple structure and through simple fabrication processes. The electric field emission cold cathode includes a sharp-pointed emitter, a gate electrode having an aperture surrounding the emitter, and a cathode electrode connected to the emitter. The electric field emission cold cathode further includes an n-type diffused layer connected to the emitter and the cathode electrode, and a p-type silicon substrate electrically connected to the cathode electrode at least at a side thereof facing the emitter. A pinch-off resistor is provided between the emitter and the cathode electrode. The pinch-off resistor has a saturation current value smaller than a short-circuit breakdown current of the emitter.

Abstract: A field emission cold cathode element designed with the objects of enabling control of overcurrents that arise at times of discharge without adding a power source or complicating the operating circuits, realizing high-frequency operation and lower power consumption without giving rise to short-circuit damage due to discharge breakdown, and moreover, suppressing increases in element temperature; wherein an n-type region underlying emitters is divided between three n-type semiconductor regions: a first n-type semiconductor region, a second n-type semiconductor region and a third n-type semiconductor region.

Abstract: A field-emission cold cathode includes a substrate having a sharply pointed emitter disposed on a surface thereof and serving as an emitter electrode, an insulating film disposed on the substrate, and a gate electrode disposed on the insulating film and having an opening defined therein and having an edge surrounding the emitter. The gate electrode and the emitter are spaced from each other across a cavity near the emitter. The insulating film and the substrate have a boundary surface therebetween which is lower than the surface of the substrate. The substrate has a step positioned between the boundary surface and the surface of the substrate on which the emitter is disposed, the step being disposed between the insulating film and the emitter. The insulating film supports the gate electrode and has a thickness greater than the distance between the emitter and the gate electrode.

Abstract: A field emission cold cathode has a plurality of emitters in a group for each gate electrode and a serial resistance layer divided into a plurality resistance layer sections each corresponding to one of the emitters. The resistance layer is divided by a deep trench filled with an insulator layer or conductive layer forming a P-N junction between the same and the resistance layer section. A linear voltage-current characteristic is obtained by a stable resistance of the resistance layer section to prevent a short-circuit failure between the emitter and the gate electrode.

Abstract: In a method of operating an electron tube including a plurality of emitters formed on a substrate and having sharp tips, gate electrodes surrounding the plurality of emitters, and a peripheral electrode surrounding an electron emission region constituted by the plurality of emitters and the gate electrodes and insulated from the plurality of emitters and the gate electrodes, the voltage applied to the peripheral electrode is set to be lower than the voltage applied to the gate electrode.

Abstract: A field emission cold cathode in which all protrusion portions and corner portions around a gate electrode as well as corner portions facing an anode electrode are formed so as to be at obtuse angles or arc-shaped, whereby discharging of the gate electrode is suppressed to prevent breakdown of the device. A dummy electrode having more acute protrusion portions of the gate electrode is provided around the gate electrode, to further suppress discharging of the gate electrode.

Abstract: A method is for use in fabricating a cold cathode comprising a sharp emitter (3) having a sharp tip that is formed on a silicon substrate 1b. The method comprises a first step of forming an intermediate emitter on the silicon substrate. The intermediate emitter has first and second emitter regions (33,34). The second emitter region is positioned under the first emitter region and has a width (diameter) larger than that of the first emitter region. The method further comprises a second step of processing the intermediate emitter into the sharp emitter by oxidation.