Patents by Inventor Hisashi Yamauchi
Hisashi Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160070200Abstract: An image forming apparatus includes: an image bearing member; a developer carrying member for carrying developer; a cartridge detachably mountable to a main assembly of the image forming apparatus, the cartridge includes a cleaning means for removing the developer remaining on the developer carrying member after a developer image is transferred onto a transfer material, a developer buffering portion for accommodating the developer removed by the cleaning portion, and a feeding member driven for feeding the developer from the developer buffering portion to a developer container provided in the main assembly; a storing portion for storing cartridge operation information; and a controller for controlling the feeding member to stop drive of the feeding member on the basis of the cartridge operation information stored in the storing portion.Type: ApplicationFiled: September 3, 2015Publication date: March 10, 2016Inventor: Hisashi Yamauchi
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Publication number: 20150125166Abstract: Provided is a technology that enhances the detection precision of the residual amount of a developer. An apparatus according to the invention includes: an accommodating portion in which a developer is accommodated; a sheet-like stirring member that, by rotating, stirs the developer accommodated in the accommodating portion; a piezoelectric element that is affixed to the stirring member and that outputs voltage when being deformed; and a deflection forming portion that comes in contact with the stirring member, thereby causing the stirring member to deflect, when a free end of the rotating stirring member is outside a developer accumulation region in the accommodating portion.Type: ApplicationFiled: October 31, 2014Publication date: May 7, 2015Inventors: Akihisa Matsukawa, Toshiya Kaino, Keisuke Mochizuki, Bunro Noguchi, Shun Sato, Masahiro Shibata, Yoshihiro Mitsui, Hisashi Yamauchi
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Publication number: 20140186062Abstract: A developer container unit includes a container containing developer and a piezoelectric film for detecting an amount of developer in the container. A sensitivity of the piezoelectric film to a stress in a direction parallel to a film surface is greater than a sensitivity of the piezoelectric film to a stress in a direction perpendicular to the film surface, and the piezoelectric film is deformable with a movement thereof relative to the developer.Type: ApplicationFiled: December 23, 2013Publication date: July 3, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Yoshihiro Mitsui, Toshiya Kaino, Keisuke Mochizuki, Bunro Noguchi, Akihisa Matsukawa, Shun Sato, Masahiro Shibata, Hisashi Yamauchi
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Patent number: 8718499Abstract: An image forming apparatus includes first and second developer carrying members and a control device. The apparatus is operable in a first mode where an image of a single color is formed using the first developer carrying member and is operable in a second mode, wherein an image of a plurality of colors is formed using the first and second developer carrying members. The control device controls a first discharging operation for discharging developer from the first developer carrying member and a second discharging operation for discharging developer from each of the first and second developer carrying members. When the apparatus executes only the first mode, the control device performs more image formations, in a period between completion of the second discharging operation and start of the first discharging operation, compared to a period between completion of the first discharging operation and start of a subsequent first discharging operation.Type: GrantFiled: May 30, 2013Date of Patent: May 6, 2014Assignee: Canon Kabushiki KaishaInventors: Kazuhiro Okubo, Masahiro Yoshida, Kazunori Hashimoto, Masahiro Shibata, Hisashi Yamauchi
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Publication number: 20130308967Abstract: An image forming apparatus includes first and second developer carrying members and a control device. The apparatus is operable in a first mode where an image of a single color is formed using the first developer carrying member and is operable in a second mode, wherein an image of a plurality of colors is formed using the first and second developer carrying members. The control device controls a first discharging operation for discharging developer from the first developer carrying member and a second discharging operation for discharging developer from each of the first and second developer carrying members. When the apparatus executes only the first mode, the control device performs more image formations, in a period between completion of the second discharging operation and start of the first discharging operation, compared to a period between completion of the first discharging operation and start of a subsequent first discharging operation.Type: ApplicationFiled: May 30, 2013Publication date: November 21, 2013Inventors: Kazuhiro Okubo, Masahiro Yoshida, Kazunori Hashimoto, Masahiro Shibata, Hisashi Yamauchi
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Patent number: 8472823Abstract: An image forming apparatus includes first and second developer carrying members and a control device. The apparatus is operable in a first mode where an image of a single color is formed using the first developer carrying member and is operable in a second mode, wherein an image of a plurality of colors is formed using the first and second developer carrying members. The control device controls a first discharging operation for discharging developer from the first developer carrying member and a second discharging operation for discharging developer from each of the first and second developer carrying members. When the apparatus executes only the first mode, the control device performs more image formations, in a period between completion of the second discharging operation and start of the first discharging operation, compared to a period between completion of the first discharging operation and start of a subsequent first discharging operation.Type: GrantFiled: January 29, 2010Date of Patent: June 25, 2013Assignee: Canon Kabushiki KaishaInventors: Kazuhiro Okubo, Masahiro Yoshida, Kazunori Hashimoto, Masahiro Shibata, Hisashi Yamauchi
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Patent number: 8428477Abstract: An image forming apparatus includes a toner carrying member for supplying toner to an image bearing member to visualize the latent image; a rotatable toner supply member, contacted to the toner carrying member, for supplying toner to the image bearing member; a voltage applying device for applying voltages to the toner carrying member and the toner supply member; and a controller for controlling the voltage applying device to control voltages applied to the toner carrying member and the toner supplying member.Type: GrantFiled: June 1, 2010Date of Patent: April 23, 2013Assignee: Canon Kabushiki KaishaInventors: Masahiro Shibata, Masahiro Yoshida, Kazunori Hashimoto, Kazuhiro Okubo, Hisashi Yamauchi
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Patent number: 8238177Abstract: Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.Type: GrantFiled: March 29, 2010Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventor: Hisashi Yamauchi
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Patent number: 8116668Abstract: A toner supplying roller which is used in a developing apparatus and has the following characteristics: (1) an average diameter of a foam cell opening portion on a surface of a foam elastic member is 100 to 800 ?m, (2) an unopened cell closed by a skin layer of a film thickness of 50 ?m or less is present in the surface of the foam elastic member, and (3) assuming that a surface area of the foam elastic member is A, a total area of the foam cell opening portions is B, and a surface area of the unopened cell is C, the following relationship is satisfied: B A + 0.2 ? B + C A ? 0.95 .Type: GrantFiled: May 22, 2009Date of Patent: February 14, 2012Assignee: Canon Kabushiki KaishaInventors: Masato Koyanagi, Shinji Katagiri, Masahiro Yoshida, Kazunori Hashimoto, Hisashi Yamauchi
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Publication number: 20100303486Abstract: An image forming apparatus includes a toner carrying member for supplying toner to the image bearing member to visualize the latent image; a rotatable toner supply member, contacted to the toner carrying member, for supplying the toner to the toner carrying member, the toner supply member including a surface foam layer; a voltage applying device for applying voltages to the toner carrying member and the toner supply member; a controller for controlling the voltage application apparatus such that A and B have a polarity which is the same as a regular charging polarity of the toner, where A=Vs2?Vd2; B=(Vs2?Vd2)?(Vs1?Vd1); Vd1 is a voltage applied to the toner carrying member during a period in which the latent image is visualized; Vs1 is a voltage applied to the toner supplying member during the period; vd2 is a voltage applied to the toner carrying member during at least a part of a period which is after the visualization of the latent image and before stoppage of rotation of the toner supplying member; and VsType: ApplicationFiled: June 1, 2010Publication date: December 2, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Masahiro Shibata, Masahiro Yoshida, Kazunori Hashimoto, Kazuhiro Okubo, Hisashi Yamauchi
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Publication number: 20100254205Abstract: Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.Type: ApplicationFiled: March 29, 2010Publication date: October 7, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Hisashi Yamauchi
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Publication number: 20100196030Abstract: An image forming apparatus includes first and second developer carrying members and a control device. The apparatus is operable in a first mode where an image of a single color is formed using the first developer carrying member and is operable in a second mode, wherein an image of a plurality of colors is formed using the first and second developer carrying members. The control device controls a first discharging operation for discharging developer from the first developer carrying member and a second discharging operation for discharging developer from each of the first and second developer carrying members. When the apparatus executes only the first mode, the control device performs more image formations, in a period between completion of the second discharging operation and start of the first discharging operation, compared to a period between completion of the first discharging operation and start of a subsequent first discharging operation.Type: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Kazuhiro Okubo, Masahiro Yoshida, Kazunori Hashimoto, Masahiro Shibata, Hisashi Yamauchi
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Publication number: 20090297230Abstract: A toner supplying roller which is used in a developing apparatus and has the following characteristics: (1) an average diameter of a foam cell opening portion on a surface of a foam elastic member is 100 to 800 ?m, (2) an unopened cell closed by a skin layer of a film thickness of 50 ?m or less is present in the surface of the foam elastic member, and (3) assuming that a surface area of the foam elastic member is A, a total area of the foam cell opening portions is B, and a surface area of the unopened cell is C, the following relationship is satisfied: B A + 0.2 ? B + C A ? 0.95 .Type: ApplicationFiled: May 22, 2009Publication date: December 3, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Masato Koyanagi, Shinji Katagiri, Masahiro Yoshida, Kazunori Hashimoto, Hisashi Yamauchi
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Patent number: 7562256Abstract: A fault diagnosis method for a semiconductor device in which a memory and a register are monolithically integrated is provided. The fault diagnosis method is composed of: first testing the memory with respect to a series of addresses to identify a first error address; externally outputting the first error address; storing the first error address into the register; second testing the memory with respect to a series of addresses; identifying a second error address different from the first error address using a result of the second testing and the first error address stored in the register; externally outputting the second error address; and updating the register to store the second error address.Type: GrantFiled: May 18, 2005Date of Patent: July 14, 2009Assignee: Nec Electronics CorporationInventor: Hisashi Yamauchi
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Patent number: 7475300Abstract: A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is completed. During the shift operation, a value for refresh operation is added to the value passing through the flip-flop for setting a value to the memory to be tested.Type: GrantFiled: July 5, 2006Date of Patent: January 6, 2009Assignee: NEC Electronics CorporationInventor: Hisashi Yamauchi
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Publication number: 20070033462Abstract: A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is completed. During the shift operation, a value for refresh operation is added to the value passing through the flip-flop for setting a value to the memory to be tested.Type: ApplicationFiled: July 5, 2006Publication date: February 8, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Hisashi Yamauchi
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Patent number: 7024606Abstract: A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.Type: GrantFiled: December 16, 2003Date of Patent: April 4, 2006Assignee: NEC Electronics CorporationInventor: Hisashi Yamauchi
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Publication number: 20050262422Abstract: A fault diagnosis method for a semiconductor device in which a memory and a register are monolithically integrated is provided. The fault diagnosis method is composed of: first testing the memory with respect to a series of addresses to identify a first error address; externally outputting the first error address; storing the first error address into the register; second testing the memory with respect to a series of addresses; identifying a second error address different from the first error address using a result of the second testing and the first error address stored in the register; externally outputting the second error address; and updating the register to store the second error address.Type: ApplicationFiled: May 18, 2005Publication date: November 24, 2005Applicant: NEC Electronics CorporationInventor: Hisashi Yamauchi
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Publication number: 20050235184Abstract: Disclosed is a semiconductor integrated circuit device using a scan path test in which propagation of an indefinite value to a test target path is inhibited while suppressing an increase in a circuit area, and a test method thereof. When a plurality of flip-flops within a logic circuit is serially connected to form scan chains and a scan path test is conducted, one or a plurality of flip-flops within the logic circuit are provided as indefinite state control flip-flops for holding values for preventing an indefinite value from propagating through a test target path and being captured by the scan chain on an output side during the test. The indefinite state control flip-flops are serially connected based on a control signal, and constitute a chain of flip-flops, different from the scan chain of other flip-flops. A value serially input from an input terminal is set in the plurality of indefinite state control flip-flops, respectively.Type: ApplicationFiled: April 19, 2005Publication date: October 20, 2005Inventor: Hisashi Yamauchi
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Publication number: 20040153930Abstract: A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.Type: ApplicationFiled: December 16, 2003Publication date: August 5, 2004Inventor: Hisashi Yamauchi