Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode.

Abstract: A scan test method may include providing initial test values to a plurality of boundary scan flip-flops (231 to 235) in a shift operation mode. In a next clock cycle, next test values may be provided to the plurality of boundary scan flip-flops (231 to 235) in the shift operation mode. A test result may be read from a device under test (241) into a plurality of boundary scan flip-flops (251 and 252) in a normal operation mode. In this way, a test may be conducted on a device under test (241) with only one operation in a normal operation mode and a test pattern may be set with reduced complexity due to normal operating circuits providing test values based on received inputs.

Abstract: A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.

Abstract: An apparatus and method for treating gas, employ a honeycomb rotor carrying an adsorbent thereon. A casing having an adsorbing zone, a plurality of desorbing zones and a purge zone houses the honeycomb rotor. A drive device rotates the honeycomb rotor in the casing. A gas movement device moves gas through the casing and the honeycomb rotor. A heater heats gas moved through the purge zone. Gas from the purge zone is moved through the plurality of desorbing zones after being heated by the heater. Gas from one of the desorbing zones is discharged. Gas from a remainder of the desorbing zones is combined with gas containing contaminants to be removed, and then moved through the adsorbing zone and the purge zone.

Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the teat clock signal in the test mode.

Abstract: An LSI tester having a path analysis means for tracing a series of connections reversely along a designated signal flow path from one of flip-flops of DUT (device under test) at which flip-flop an inconsistency in pattern value has been detected as a consistency detection point by an output pattern comparator, based on circuit information in DUT, and for identifying firstly reachable flip-flops or external terminals from the inconsistency detection point as arrival points. And a sequence-pattern-inverting means sequentially inverts at least partly the values of successive test patterns one at a time with respect to each of the arrival points. The fault position in DUT is narrowed down from the arrival points simply in a shorter time.

Abstract: A CMOS integrated circuit is tested by creating a database in which types of CMOS functional units of the integrated circuit are mapped to values of quiescent power supply currents which would flow through the functional units corresponding to all possible internal states of the integrated circuit. A test pattern is applied to a simulation model of the functional units of the integrated circuits and an output is detected therefrom. Corresponding to the output of the simulation model, values of the quiescent power supply currents are read from the database and a decision threshold is derived from a total sum of the read values. A power supply current of the integrated circuit is then measured while subjecting it to the test pattern and the measured current is compared with the decision threshold to produce a test result of the integrated circuit.

Abstract: In a scan path so configured that a series of tests using a scan path are performed by a scan shift of shifting the data of a scan path flipflop and a normal circuit test of testing a circuit for a normal operation by using the shifted data, and that at the time of the scan path testing, the scan path flipflop fetches data at a first timing and outputs the fetched data at a second timing, there is provided a scan path test control circuit which includes a control circuit so constructed to generate a logical value which never either sets or resets the scan path flipflop at the time of the scan shifting, and a logical value of validating a normal logic which sets or resets the scan path flipflop after the scan shifting. The test control circuit also generates, at the time of the normal test, a logic value which neither sets nor resets the scan path flipflop in synchronism with a timing signal between the first timing after the data is fetched and the second timing.

Abstract: A cassette loading device for a cassette recording apparatus includes a cylindrical cassette magazine having a plurality of radially directed slots, each adapted to contain a tape cassette, and narrow slits along the circumferential periphery thereof for receiving paper slips, each slip having information thereon concerning the recording of a tape cassette in a respective slot; a drive device for intermittently rotating the cassette magazine so that the radially directed slots are successively disposed at a cassette laoding position; a detecting apparatus for detecting the presence of a paper slip in the slit which is retarded by one step with respect to the slit corresponding to the radially directed slot at the cassette loading position and for generating an output signal in response thereto; and a circuit responsive to the output signal for preventing the intermittent rotation of the cassette magazine by the drive device.