Patents by Inventor Hisataka Hayashi

Hisataka Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388544
    Abstract: There are provided a substrate processing apparatus and a substrate processing method realizing an effective reduction of a voltage change of a substrate on an electrode to reduce the variation of incident energy of ions entering the substrate. The substrate processing apparatus includes: a first electrode holding a substrate on a main surface of the first electrode; a second electrode facing the first electrode; a RF power source applying to the first electrode a RF voltage whose frequency is equal to or higher than 40 MHz; and a pulse voltage applying unit applying to the first electrode a pulse voltage decreasing in accordance with a lapse of time, by superimposing the pulse voltage on the RF voltage.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 20, 2019
    Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Limited
    Inventors: Akio Ui, Hisataka Hayashi, Takeshi Kaminatsui, Shinji Himori, Norikazu Yamada, Takeshi Ohse, Jun Abe
  • Patent number: 10381198
    Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Akio Ui, Hisataka Hayashi, Kazuhiro Tomioka, Hiroshi Yamamoto, Tsubasa Imamura
  • Patent number: 10332906
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori Narumiya, Hisataka Hayashi, Keisuke Kikutani, Akio Ui, Yosuke Sato
  • Publication number: 20180145086
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Application
    Filed: July 27, 2017
    Publication date: May 24, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori NARUMIYA, Hisataka HAYASHI, Keisuke KIKUTANI, Akio UI, Yosuke SATO
  • Publication number: 20170186589
    Abstract: A plasma processing apparatus of an embodiment includes a chamber, an introducing part, a substrate electrode, a high-frequency power source, a low-frequency power source, and a switching mechanism. The introducing part introduces a process gas into the chamber. The substrate electrode is disposed in the chamber, a substrate is directly or indirectly mounted on the substrate electrode, and the substrate electrode includes a first and a second electrode elements alternately arranged. The high-frequency power source outputs a high-frequency voltage of 40 MHz or more for ionizing the process gas to generate plasma. The low-frequency power source outputs a low-frequency voltage of 20 MHz or less for introducing ions from the plasma. The switching mechanism applies the low-frequency voltage alternately to the first and the second electrode elements.
    Type: Application
    Filed: March 17, 2017
    Publication date: June 29, 2017
    Inventors: Yosuke SATO, Akio UI, Hisataka HAYASHI
  • Publication number: 20170169996
    Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 15, 2017
    Inventors: Akio UI, Hisataka HAYASHI, Kazuhiro TOMIOKA, Hiroshi YAMAMOTO, Tsubasa IMAMURA
  • Patent number: 9583360
    Abstract: In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Ui, Hisataka Hayashi, Keisuke Kikutani
  • Publication number: 20160027619
    Abstract: A plasma processing apparatus of an embodiment includes a chamber, an introducing part, a substrate electrode, a high-frequency power source, a low-frequency power source, and a switching mechanism. The introducing part introduces a process gas into the chamber. The substrate electrode is disposed in the chamber, a substrate is directly or indirectly mounted on the substrate electrode, and the substrate electrode includes a first and a second electrode elements alternately arranged. The high-frequency power source outputs a high-frequency voltage of 40 MHz or more for ionizing the process gas to generate plasma. The low-frequency power source outputs a low-frequency voltage of 20 MHz or less for introducing ions from the plasma. The switching mechanism applies the low-frequency voltage alternately to the first and the second electrode elements.
    Type: Application
    Filed: July 21, 2015
    Publication date: January 28, 2016
    Inventors: Yosuke SATO, AKIO UI, HISATAKA HAYASHI
  • Patent number: 9111875
    Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
  • Publication number: 20150162223
    Abstract: There are provided a substrate processing apparatus and a substrate processing method realizing an effective reduction of a voltage change of a substrate on an electrode to reduce the variation of incident energy of ions entering the substrate. The substrate processing apparatus includes: a first electrode holding a substrate on a main surface of the first electrode; a second electrode facing the first electrode; a RF power source applying to the first electrode a RF voltage whose frequency is equal to or higher than 40 MHz; and a pulse voltage applying unit applying to the first electrode a pulse voltage decreasing in accordance with a lapse of time, by superimposing the pulse voltage on the RF voltage.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Akio UI, Hisataka HAYASHI, Takeshi KAMINATSUI, Shinji HIMORI, Norikazu YAMADA, Takeshi OHSE, Jun ABE
  • Publication number: 20150011089
    Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 8, 2015
    Inventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
  • Patent number: 8840753
    Abstract: The present invention is a plasma etching method including: an arranging step of arranging a pair of electrodes oppositely in a chamber and making one of the electrodes support a substrate to be processed in such a manner that the substrate is arranged between the electrodes, the substrate having an organic-material film and an inorganic-material film; and an etching step of applying a high-frequency electric power to at least one of the electrodes to form a high-frequency electric field between the pair of the electrodes, supplying a process gas into the chamber to form a plasma of the process gas by means of the electric field, and selectively plasma-etching the organic-material film of the substrate with respect to the inorganic-material film by means of the plasma; wherein a frequency of the high-frequency electric power applied to the at least one of the electrodes is 50 to 150 MHz in the etching step.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: September 23, 2014
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Masanobu Honda, Kazuya Nagaseki, Koichiro Inazawa, Shoichiro Matsuyama, Hisataka Hayashi
  • Patent number: 8821744
    Abstract: A substrate processing method using a substrate processing apparatus includes a first step and a second step. The first step is to apply a negative voltage pulse from a pulsed power supply to be included in the apparatus. The second step is to apply floating potential for an interval of time between the negative voltage pulse and a positive voltage pulse from the pulsed power supply subsequent to the negative voltage pulse. In addition, the apparatus includes a chamber, a first electrode, a second electrode, an RF power supply, and the pulsed power supply. The second electrode is provided so that the second electrode faces the first electrode to hold a substrate. The RF power supply applies an RF voltage having a frequency of 50 MHz or higher to the second electrode. The pulsed power supply repeatedly applies a voltage waveform with the RF voltage to the second electrode.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Ui, Hisataka Hayashi
  • Patent number: 8821684
    Abstract: A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 2, 2014
    Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Limited
    Inventors: Akio Ui, Naoki Tamaoki, Takashi Ichikawa, Hisataka Hayashi, Takeshi Kaminatsui, Shinji Himori, Norikazu Yamada, Takeshi Ohse, Jun Abe
  • Publication number: 20140083977
    Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akio UI, Hisataka Hayashi, Kazuhiro Tomioka, Hiroshi Yamamoto, Tsubasa Imamura
  • Publication number: 20130344698
    Abstract: According to one embodiment, a mask layer is formed on a film to be processed. A resist film containing a desired pattern is formed on the mask layer. Etching is performed on the above mentioned mask layer with an etching gas that does not contain fluorine. The method also includes removing the resist film. After the resist film is removed, using the mask layer as a mask, an etching is performed on the to be processed film using a fluorocarbon gas.
    Type: Application
    Filed: March 4, 2013
    Publication date: December 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke OCHIAI, Hisataka HAYASHI, Yusuke KASAHARA
  • Patent number: 8545670
    Abstract: A plasma processing apparatus for processing a substrate using plasma includes a first electrode configured to mount the substrate, a second electrode disposed to face the first electrode with a predetermined space, a chamber containing the first electrode and the second electrode, the chamber being capable of adjusting an inside atmosphere, a first electric power source device configured to apply a first RF voltage for controlling a self-bias voltage generated on the substrate to the first electrode, the first electric power source device applying a substantially constant width and a substantially constant value in a peak-to-peak voltage of an RF voltage of a first frequency at intervals, and a second electric power source device configured to apply a second RF voltage of a second frequency for generating plasma between the first and second electrodes to one of the first electrode and the second electrode.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hisataka Hayashi, Akio Ui
  • Patent number: 8536061
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
  • Patent number: 8524609
    Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Inada, Mitsuhiro Omura, Hisataka Hayashi
  • Publication number: 20120228263
    Abstract: In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 13, 2012
    Inventors: Akio UI, Hisataka Hayashi, Keisuke Kikutani