Patents by Inventor Hisayo Momose
Hisayo Momose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6642560Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: June 4, 2002Date of Patent: November 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20020185676Abstract: A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel forming region on the (100) surface orientation.Type: ApplicationFiled: July 30, 2001Publication date: December 12, 2002Inventor: Hisayo Momose
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Publication number: 20020145157Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: June 4, 2002Publication date: October 10, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6410952Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: April 9, 2001Date of Patent: June 25, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20010042873Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: April 9, 2001Publication date: November 22, 2001Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6229164Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: November 16, 1999Date of Patent: May 8, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 5990516Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (T.sub.OX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (L.sub.g) of the gate electrode (2) is determined to be equal to or less than 0.3 .mu.m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: September 13, 1995Date of Patent: November 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 5955761Abstract: A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.Type: GrantFiled: April 30, 1998Date of Patent: September 21, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Hiroshi Iwai, Masanobu Saito, Hisayo Momose, Tatsuya Ohguro, Mizuki Ono
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Patent number: 5903027Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: August 13, 1997Date of Patent: May 11, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5898203Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: July 30, 1997Date of Patent: April 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5780901Abstract: A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.Type: GrantFiled: June 30, 1995Date of Patent: July 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Hiroshi Iwai, Masanobu Saito, Hisayo Momose, Tatsuya Ohguro, Mizuki Ono
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Patent number: 5766965Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: December 5, 1994Date of Patent: June 16, 1998Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5698881Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: December 2, 1994Date of Patent: December 16, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5434440Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: May 28, 1993Date of Patent: July 18, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5198692Abstract: In a semiconductor device including a bipolar transistor having a base region formed in a collector region, and an emitter region formed in the base region, the emitter region comprises a high concentration region in contact with the base region, and a low concentration region provided between the base region and the high concentration region. The low concentration region is formed by introducing an impurity with a mask including a large opening. In addition, the high concentration region is formed by introducing an impurity with a mask including a small opening.Type: GrantFiled: June 14, 1991Date of Patent: March 30, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Hisayo Momose
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Patent number: 5106782Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact.Type: GrantFiled: July 12, 1989Date of Patent: April 21, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Matsuno, Hideki Shibata, Kazuhiko Hashimoto, Hisayo Momose