Patents by Inventor Hitesh Chawla
Hitesh Chawla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250111875Abstract: A memory system includes a memory array with first dummy read cells that discharge a dummy bit line, each of the first dummy read cells including a transistor coupled between the dummy bit line and a first ground node that is connected to a ground reference. Second dummy read cells discharge the dummy bit line, each of the dummy read cells including a transistor coupled between the dummy bit line and a second ground node. The dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal. Read circuitry retrieves data from a selected row in the memory array during a read operation, in response to the self-timing signal. Ground generation circuitry connects the second ground node to the ground reference or allows the second ground to float, based upon a control signal.Type: ApplicationFiled: August 26, 2024Publication date: April 3, 2025Applicant: STMicroelectronics International N.V.Inventors: Sant Swaroop SHRIVASTAVA, Hitesh CHAWLA, Mohd Javed IKHLAS, Sachin GULYANI
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Publication number: 20250069678Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: November 7, 2024Publication date: February 27, 2025Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Patent number: 12170120Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: GrantFiled: July 28, 2023Date of Patent: December 17, 2024Assignee: STMicroelectronics International N.V.Inventors: Hitesh Chawla, Tanuj Kumar, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori, Manuj Ayodhyawasi, Nitin Chawla, Promod Kumar
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Publication number: 20240143239Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.Type: ApplicationFiled: October 12, 2023Publication date: May 2, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Manuj AYODHYAWASI, Nitin CHAWLA
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Publication number: 20240112748Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.Type: ApplicationFiled: July 31, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Tanuj KUMAR, Hitesh CHAWLA, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240071546Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240069096Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.Type: ApplicationFiled: July 31, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Patent number: 10733453Abstract: The present disclosure provides a computer-implemented method and system for performing real time supervised detection of televised video ads in a media content of a broadcasted channel. The method includes reception of the media content and selection of a set of frames per second from the media content. The method includes extraction of keypoints from each selected frame and derivation of binary descriptors from extracted keypoints. The method includes assignment of weight value to each binary descriptor and creation of a special pyramid of the binary descriptors. The method includes obtaining a first vocabulary of binary descriptors for each selected frame and accessing a second vocabulary of binary descriptors. The method includes comparison of each binary descriptor in the first vocabulary with binary descriptors in second vocabulary and progressively scoring each selected frame of the media content. The method includes detection of a first ad in the media content.Type: GrantFiled: June 7, 2018Date of Patent: August 4, 2020Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 10719714Abstract: The present disclosure provides a computer-implemented method and system for adaptively reducing detection time in real time supervised detection of televised ads in media content of a channel. The method includes reception of the media content and selection of a set of frames per second from the media content. The method includes extraction of keypoints from each selected frame and derivation of binary descriptors from extracted keypoints. The method includes assignment of weight value to each binary descriptor and creation of a special pyramid of the binary descriptors. The method includes obtaining a first vocabulary of binary descriptors for each selected frame and accessing a second vocabulary of binary descriptors. The method includes comparison of each binary descriptor in the first vocabulary with binary descriptors in second vocabulary. The method includes progressively scoring each selected frame of the media content and detecting a first ad in the media content.Type: GrantFiled: June 7, 2018Date of Patent: July 21, 2020Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 10719715Abstract: The present disclosure provides a computer-implemented method and system for adaptively switching supervised detection strategy for watermarked and non-watermarked real time televised video advertisements. The televised video advertisements are present in a live stream of a media content of a broadcasted channel. The method includes selection of a set of frames per second from the media content. The method includes checking for one or more watermarked features in each selected frame of the media content. The method includes switching to a first detection strategy. The first detection strategy is associated with detection of a first ad in the live stream of the media content when the one or more watermarked feature are present in each checked frame in the selected set of frames.Type: GrantFiled: June 7, 2018Date of Patent: July 21, 2020Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 10713496Abstract: The present disclosure provides a computer-implemented method and system for hardware, channel, language and ad length agnostic detection of multi-lingual televised advertisements. The detection is performed across live streams of media content of one or more broadcasted channels. The method includes selection of a set of frames per second from a pre-defined set of frames. The method includes extraction of a pre-defined number of keypoints from each selected frame and derivation of a pre-defined number of binary descriptors from the extracted keypoints. The method includes creation of a special pyramid of the binary descriptors and accessing a second vocabulary of binary descriptors. The method includes comparison of each spatially identifiable binary descriptor from the first vocabulary with spatially identifiable binary descriptors in clusters of the second vocabulary. The method includes progressively scoring each selected frame and detection of the first ad in the live streams of the media content.Type: GrantFiled: June 7, 2018Date of Patent: July 14, 2020Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Publication number: 20180359523Abstract: The present disclosure provides a computer-implemented method and system for progressive penalty and reward based ad scoring for real time supervised detection of televised video ads in televised media content. The method includes reception of the media content and selection of a set of frames per second from the media content. The method includes extraction of key points from each selected frame and derivation of binary descriptors from extracted key points. The method includes assignment of weight value to each binary descriptor and creation of a special pyramid of the binary descriptors. The method includes obtaining a first vocabulary of binary descriptors for each selected frame and accessing a second vocabulary of binary descriptors. The method includes comparison of each binary descriptor in the first vocabulary with binary descriptors in second vocabulary. The method includes progressively scoring each selected frame of the media content for detection of a first ad.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Debasish MITRA, Hitesh CHAWLA
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Publication number: 20180357488Abstract: The present disclosure provides a computer-implemented method and system for performing real time supervised detection of televised video ads in a media content of a broadcasted channel. The method includes reception of the media content and selection of a set of frames per second from the media content. The method includes extraction of keypoints from each selected frame and derivation of binary descriptors from extracted keypoints. The method includes assignment of weight value to each binary descriptor and creation of a special pyramid of the binary descriptors. The method includes obtaining a first vocabulary of binary descriptors for each selected frame and accessing a second vocabulary of binary descriptors. The method includes comparison of each binary descriptor in the first vocabulary with binary descriptors in second vocabulary and progressively scoring each selected frame of the media content. The method includes detection of a first ad in the media content.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Debasish MITRA, Hitesh CHAWLA
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Publication number: 20180357489Abstract: The present disclosure provides a computer-implemented method and system for adaptively reducing detection time in real time supervised detection of televised ads in media content of a channel. The method includes reception of the media content and selection of a set of frames per second from the media content. The method includes extraction of keypoints from each selected frame and derivation of binary descriptors from extracted keypoints. The method includes assignment of weight value to each binary descriptor and creation of a special pyramid of the binary descriptors. The method includes obtaining a first vocabulary of binary descriptors for each selected frame and accessing a second vocabulary of binary descriptors. The method includes comparison of each binary descriptor in the first vocabulary with binary descriptors in second vocabulary. The method includes progressively scoring each selected frame of the media content and detecting a first ad in the media content.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Debasish MITRA, Hitesh CHAWLA
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Publication number: 20180357490Abstract: The present disclosure provides a computer-implemented method and system for adaptively switching supervised detection strategy for watermarked and non-watermarked real time televised video advertisements. The televised video advertisements are present in a live stream of a media content of a broadcasted channel. The method includes selection of a set of frames per second from the media content. The method includes checking for one or more watermarked features in each selected frame of the media content. The method includes switching to a first detection strategy. The first detection strategy is associated with detection of a first ad in the live stream of the media content when the one or more watermarked feature are present in each checked frame in the selected set of frames.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Debasish MITRA, Hitesh CHAWLA
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Publication number: 20180357491Abstract: The present disclosure provides a computer-implemented method and system for hardware, channel, language and ad length agnostic detection of multi-lingual televised advertisements. The detection is performed across live streams of media content of one or more broadcasted channels. The method includes selection of a set of frames per second from a pre-defined set of frames. The method includes extraction of a pre-defined number of keypoints from each selected frame and derivation of a pre-defined number of binary descriptors from the extracted keypoints. The method includes creation of a special pyramid of the binary descriptors and accessing a second vocabulary of binary descriptors. The method includes comparison of each spatially identifiable binary descriptor from the first vocabulary with spatially identifiable binary descriptors in clusters of the second vocabulary. The method includes progressively scoring each selected frame and detection of the first ad in the live streams of the media content.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Debasish MITRA, Hitesh CHAWLA
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Patent number: 10149022Abstract: A system and method for automated tagging of one or more advertisements broadcasted on a channel in real time includes a step of detecting the one or more advertisements broadcasted on the channel, and another step of fetching a set of prominent frames and a pre-defined section of an audio clip. The set of prominent frames and the pre-defined section of the audio clip correspond to a detected advertisement. The method also includes another step of retrieving plural features. The plural features corresponds to the set of prominent frames and the pre-defined section of the audio clip. The method also includes another step of comparing each of the plurality of features with corresponding pre-defined set of features. The method also includes another step of tagging the detected advertisement with a unique tag.Type: GrantFiled: March 9, 2017Date of Patent: December 4, 2018Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 10117000Abstract: A system and method for hardware agnostic detection of one or more advertisements broadcasted across one or more channels includes extracting a first set of audio fingerprints and a first set of video fingerprints. The method also includes generating a set of digital signature values corresponding to an extracted set of video fingerprints, and normalizing each frame of a pre-determined number of frames of a video. The method also includes scaling each frame of the corresponding pre-determined number of frames of the video clip to a pre-defined scale. Each frame corresponds to the broadcasted media content on the channel. The method also includes trimming a first pre-defined region and a second pre-defined region of each frame by a pre-defined percentage of a frame width, a frame height and a pre-defined number of pixels in each frame.Type: GrantFiled: March 9, 2017Date of Patent: October 30, 2018Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 9894412Abstract: A system and method for detecting one or more advertisements broadcasted on a channel in real time includes a step of receiving a live feed, with the live feed being associated with a media content broadcast on the channel in real time. The method also includes a step of deriving one or more characteristics associated with one or more properties associated with the channel. The method also includes a step of analyzing the one or more characteristics associated with the one or more properties. There is also a step of matching the derived one or more characteristics associated with the one or more properties with the stored one or more characteristics associated with the one or more properties. The method also includes a step of detecting the one or more advertisements broadcasted on the channel in real time.Type: GrantFiled: March 9, 2017Date of Patent: February 13, 2018Assignee: Silveredge Technologies Pvt. Ltd.Inventors: Debasish Mitra, Hitesh Chawla
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Patent number: 9865333Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.Type: GrantFiled: April 19, 2016Date of Patent: January 9, 2018Assignee: STMicroelectronics International N.V.Inventors: Kedar Janardan Dhori, Ashish Kumar, Hitesh Chawla, Praveen Kumar Verma