Abstract: A graphics processing system includes a graphics processor for carrying out image processing, a control processor for use in producing a draw ready signal to enable the image processing, and a time counter for use in determining a process time for the image processing. The graphics processor begins execution of the image processing in response to the reception of the draw ready signal and produces a draw complete signal upon completion of the image processing. The draw complete signal represents the completion of the image processing. The time counter begins determination of the execution load on the processor in response to the reception of the draw ready signal and terminates the determination in response to the reception of the draw complete signal. This makes it possible to determine the process time from the beginning to the end of the image processing.

Abstract: The present invention provides data communication technology for improving the efficiency of cooperation of two or more information processing units (GSM) for more sophisticated processing. According to the present invention, there are provided four GSMs, a sub-MG (merger) for merging data output from the GSMs, and a main MG for merging data output from the four sub-MGs. Data output from the GSMs are stored in parallel in a register on a unit length basis. Then the data stored in the register are serially read on the unit length basis to form serial data. When the serial data contain altered data, auxiliary data for identifying which data have been altered or modified are added to a predetermined portion of the serial data. Then the serial data with the auxiliary data added thereto are output to the main MG. On the other hand, parallel data to be output from a main SYNC to each GSM are copied, and the copies of the same parallel data are propagated over all the GSMs at the same time.

Abstract: The present invention provides data processing technology for making two or more processing units cooperate with one another. According to the present invention, output data from processing units (GSM) are merged by each sub-MG (merger). Output data from the sub-MGs are merged by a main MG, and the merged output data are displayed on a display unit. Each GSM initiates drawing processing assigned thereto, in response to the reception of a drawing enable signal, and after execution of the processing, it outputs a drawing end signal. The GSMs to which the drawing enable signal is to be sent and the GSMs from which the drawing end signal is to be received are set for each application. A main SYNC sends the drawing enable signal to corresponding GSMs in the order of setting for an application in response to the reception of a processing request from the application, while it receives the drawing end signal from the corresponding GSMs so that the processing results of the GSMs will be displayed on the display unit.

Abstract: An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon

Abstract: An input matching circuit is provided having the output impedance-frequency characteristics wherein the output impedance shows a value approximately equal to that of the gate input impedance of the FET at the frequency of the objective signal to be amplified, and the output impedance shows a value not more than twice the gate input impedance of the FET at least at the entire frequencies from the frequency of the objective signal to be amplified through twice the frequency of the objective signal to be amplified so that the matching between the input previous stage circuit and the gate of the FET can be secured. Thereby, a high-frequency power amplifier circuit and a high-frequency power amplifier module, which can suppress the occurrence of distortion, perform stably, and get miniaturized, are configured.

Abstract: An image processing unit is provided to solve the problem of an aliasing usually occurred when a foreground image and a background image are synthesized by using a key signal; this image processing unit comprises: an image filter circuit that applies to the foreground image an anti-aliasing processing to make obscure an aliasing that displays a slant graphic border in a stepped indentation due to an insufficiency of the number of pixels; a key filter circuit that applies the anti-aliasing processing to the key signal; and a pixel detection circuit that detects a pixel having a possibility to generate a color mixture by an operation of the image filter circuit from the key signal and a size of the image filter circuit. In this construction, the image filter circuit applies an anti-aliasing processing using only the pixel that constitutes the foreground image and does not contain a background color to the pixel having a possibility to generate the color mixture that the pixel detection circuit detects.

Abstract: A method differentiates simultaneous and sequential key strokes by detecting simultaneous key strokes if two keys are pushed within a judging time T.sub.L. The method includes the steps of (a) measuring a first time T.sub.1 from a time when a first key is pushed to a time when a second key is pushed, and a second time T.sub.2 from the time when the second key is pushed to a time when one of the first and second keys is released, (b) comparing the first and second times T.sub.1 and T.sub.2 with an arbitrary threshold function T.sub.C which is set within the judging time T.sub.L, and (c) differentiating whether key strokes of the first and second keys are simultaneous or sequential based on a comparison result of the step (b).