Abstract: A system LSI dynamically and speedily controls clocks of various frequencies as used in a wide range of operation modes from high-speed to low-speed operation modes, enabling user selection of a system of power consumption type most suitable. The system LSI includes a ROM that stores a clock control library for carrying out clock state transitions between ordinary operation modes; and a system control circuit having a register for carrying out clock state transitions between ordinary operation modes and special modes responsive to changes in value of the register, and also carrying out clock state transitions among ordinary operation modes responsive to the clock control library. Calling of the clock control library and changing of the register value are controlled by an application program. The main library of the clock control library is described and called using C language.

Abstract: The invention of the present application provides an isolated and purified human mitochondrial protein comprising the amino acid sequence of SEQ ID NO: 2 or SEQ ID NO: 4, which is a novel human protein promoting aggregation and fusion of mitochondria. The present invention also provides a polynucleotide encoding such a mitochondrial protein, antibody against such a mitochondrial protein, and a proteoliposome composed of such a mitochondrial protein and lipid. Mitochondrial proteins are useful for clarifying causes of mitochondrial diseases as well as for developing preventive and therapeutic methods thereof. Furthermore, antibodies and probes derived from genes encoding such proteins are potentially useful materials for diagnosis of condition of mitochondria in particular diseases. Furthermore, proteoliposomes provide measures for specific transfer of foreign genes or drugs targeted toward mitochondria.

Abstract: In a test method of a memory IC function, memory ICs of different types are prepared after a memory tester is prepared. The data related to each test method of these memory ICs is transmitted to the memory tester. Further, after a random number is generated, a test of a predetermined memory IC is executed in reply to the generated random number. It is checked whether the tests of all the memory ICs are finished or not: and the generation of the random number and the execution of the test are repeated when they are not finished, while the processing is finished when they are finished.

Abstract: An information delivering device includes: a conversation relaying section for relaying conversation data for a conversation of an information terminal used by a user U with an information terminal used by other party P, between both of the information terminals; and an additional information delivering section for adding audio data such as advertisement and music to the conversation data so that the audio data and the conversation data can be reproduced simultaneously, while the conversation relaying section sends the conversation data from the information terminal used by the other party P to the information terminal used by the user U. This allows the information delivering device to deliver additional information such as advertisement and music by sound during a telephone conversation.

Abstract: There is disclosed a system LSI capable of dynamically and speedily controlling clocks of various frequencies as used in the wide range of operation mode, from the high-speed operation mode to the low-speed one and, in addition, enabling the user to select a system of the low power consumption type, which is most suitable for his own system. The system LSI includes a ROM 551 storing a clock control library for carrying out the clock state transition between the ordinary operation modes, and a system control circuit 534 having a register and carrying out the clock state transition between the ordinary operation mode and the special mode in response to the change of the value of the register, and also carrying out the clock state transition among the ordinary operation modes in response to the clock control library.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

Abstract: An identifying method of the present invention is to indicate and confirm identification with ease. A communication terminal device sends communication data and a communication discrimination code, to which a certification mark to identify a user of the communication terminal device has been added, as data indicating a sender. While, an identification confirming device receives the communication data and the communication discrimination code accompanied with the communication data, so as to extract the certification mark from the communication discrimination code. Thus, the user of the communication terminal device who is the sender can indicate identification, which identifies the user, without performing a special operation. While, a receiver can confirm the identification of the sender only by extracting the certification mark from the communication discrimination code in accordance with an identification confirming device.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.