Patents by Inventor Hitoshi Kume
Hitoshi Kume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6243290Abstract: The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput.Type: GrantFiled: August 25, 2000Date of Patent: June 5, 2001Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hideaki Kurata, Naoki Kobayashi, Takashi Kobayashi, Katsutaka Kimura, Hitoshi Kume, Shunichi Saeki
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Patent number: 6211546Abstract: A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer.Type: GrantFiled: December 22, 1998Date of Patent: April 3, 2001Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Hitoshi Kume, Shoji Shukuri
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Patent number: 6201735Abstract: Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.Type: GrantFiled: July 29, 1999Date of Patent: March 13, 2001Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 6181600Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 29, 1999Date of Patent: January 30, 2001Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corporation, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6157576Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 10, 1999Date of Patent: December 5, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6101123Abstract: Each memory cell of a nonvolatile semiconductor memory essentially consisting of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.Type: GrantFiled: April 8, 1999Date of Patent: August 8, 2000Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 6016273Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 27, 1996Date of Patent: January 18, 2000Assignee: Hitachi, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5991200Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 6, 1995Date of Patent: November 23, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5959894Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 17, 1998Date of Patent: September 28, 1999Assignees: Hitachi, Ltd., Hitachi USLI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5949715Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 27, 1996Date of Patent: September 7, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5932909Abstract: A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer.Type: GrantFiled: May 5, 1997Date of Patent: August 3, 1999Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Hitoshi Kume, Shoji Shukuri
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Patent number: 5917752Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 1, 1995Date of Patent: June 29, 1999Assignees: Hitachi, Ltd., Hitachi VSLI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5910913Abstract: Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.Type: GrantFiled: July 30, 1998Date of Patent: June 8, 1999Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
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Patent number: 5904518Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode.Type: GrantFiled: June 30, 1997Date of Patent: May 18, 1999Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5844842Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: May 26, 1994Date of Patent: December 1, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5828600Abstract: Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.Type: GrantFiled: October 30, 1996Date of Patent: October 27, 1998Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume
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Patent number: 5814543Abstract: A method for fabricating a semiconductor integrated circuit device comprising a nonvolatile memory cell, comprises the steps of forming a first gate material which comprises a silicon film containing no impurities, whose top surface is covered with an oxidation-resistant mask, and whose width in the gate-length direction is prescribed, on part of the surface of a first gate insulating film, forming a thermal-oxidation insulating film on the surface of an active region of a semiconductor substrate through thermal oxidation, removing an oxidation-resistant mask, forming a second gate material which comprises a silicon film into which impurities are introduced and whose width in the gate-length direction is prescribed, on each surface of the thermal-oxidation insulating film and the first gate material forming a second gate insulating film on the surface of the second gate material, and forming a third gate material on the surface of the second gate insulating film.Type: GrantFiled: November 22, 1995Date of Patent: September 29, 1998Assignee: Hitachi, Ltd.Inventors: Toshiaki Nishimoto, Shoji Shukuri, Tsutomu Okazaki, Hideo Tobe, Kazuhiro Komori, Masataka Kato, Hitoshi Kume
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Patent number: 5793678Abstract: On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and electrically isolated, from the substrate, and a MOS transistor, used as a nonvolatile memory cell, forming a drain region and a source region respectively within the well layer is used as a memory cell. Well layers associated with different columns are connected to each other by a well wiring commonly so that operation voltage different from that of the semiconductor substrate is applied thereto. In the case of data erasing, prescribed positive voltage is applied to a well wiring, and prescribed voltage lower than said positive voltage is applied to a selected word line. In the case of data programming, prescribed negative voltage is applied to the well wiring, prescribed voltage higher than said negative voltage is applied to the selected word line.Type: GrantFiled: April 5, 1996Date of Patent: August 11, 1998Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Hitoshi Kume, Takashi Kobayashi
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Patent number: 5781476Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 1, 1995Date of Patent: July 14, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 5672529Abstract: A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer.Type: GrantFiled: March 30, 1995Date of Patent: September 30, 1997Assignee: Hitachi, Ltd.Inventors: Masataka Kato, Tetsuo Adachi, Hitoshi Kume, Shoji Shukuri