Abstract: A method of manufacturing a semiconductor memory device having non-volatile memory elements or memory cells of a single-element type. The method provides for the formation of a floating gate electrode on a main surface of a semiconductor substrate and a control gate electrode on the floating gate electrode via a second gate insulating film. In accordance with the method, an impurity is introduced in self-alignment with one of a pair of opposing end portions of the control gate electrode to form a first semiconductor region, and on the second of the opposing end portions of the control gate electrode of the memory cell, the same impurity, for example, arsenic, but, however, of a lower dose is introduced in self-alignment to form a second semiconductor region.

Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

Abstract: Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

Abstract: In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.

Abstract: A semiconductor integrated circuit is provided which includes a charge pump circuit for forming a step-up (boost) voltage higher than a desired internal voltage, a voltage dividing circuit which forms a plurality of divided voltages based on a reference voltage, and a control circuit which intermittently operates the charge pump circuit so that an output voltage of the charge pump circuit provides the desired internal voltage obtained by adding a voltage obtained by multiplying a particular voltage among the plurality of divided voltages by n to a predetermined divided voltage.

Abstract: An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.

Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

Abstract: A semiconductor nonvolatile memory device capable of reducing the overhead time of the time required for switching the verify operation and the verify operation itself. In the semiconductor nonvolatile memory device which operates to program the threshold of the memory cells on the basis of a plurality of repetitive operations, the mincing width .increment.Vth of the variation of the threshold of the memory cells relative to one operation for changing the threshold (applying the program pulse) is expressed by .increment.Vth=Kvth.multidot.log (t2/t1), and the ratio (t2/t1) between the program pulse widths is expressed by (t2/t1)=10E(.increment.Vth/Kvth). The pulses in which the difference .increment.Vth of the variation of the threshold of the memory cells is made constant, and the pulse width is increased as the repetition number increases are applied to the memory cells, thereby reducing the application number of program pulses.

Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

Abstract: A semiconductor nonvolatile memory device in which the states of memory cells are determined with respect to each of all data lines in a nonvolatile memory device so as to perform control such as continuation and suspension of programming automatically. Memory cell arrays in which nonvolatile semiconductor memory cells are arranged in an array form, word lines W1 and W2 to which control gates of a plurality of memory cell groups (sectors) are connected in common and data lines to which drains of a plurality of memory cells are connected in common are included, and there are possessed of a precharging circuit, a data hold circuit having a sense amplifier function and a data latch function and a memory cell state detecting circuit for each of said data lines. Reprogramming is made at the same time with respect to memory cells (sector) connected to the same word line.

Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Abstract: Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.

Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

Abstract: A transparent lactic acid bacteria drink, which is a fermentation product obtained by allowing kefir fungi to ferment a milk material under forced supply of an oxygen-containing gas, comprises a casein protein-free whey component as the major component together with 3 to 20% of nonfat milk solids and 0.1 to 1.5% of ethanol, is disclosed. This lactic acid bacteria drink can be produced by a process which comprises allowing kefir fungi to ferment a milk material under forced supply of an oxygen-containing gas, removing a precipitate including casein protein and then sterilizing the supernatant by filtering or pasteurizing the same by heating.