Patents by Inventor Hitoshi KUNITAKE
Hitoshi KUNITAKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12087863Abstract: A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.Type: GrantFiled: May 25, 2020Date of Patent: September 10, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hitoshi Kunitake, Kazuaki Ohshima
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Publication number: 20240298447Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.Type: ApplicationFiled: May 8, 2024Publication date: September 5, 2024Inventors: Hiromichi GODO, Hitoshi KUNITAKE, Kazuki TSUDA
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Patent number: 12082391Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.Type: GrantFiled: September 25, 2020Date of Patent: September 3, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoru Ohshita, Hitoshi Kunitake, Kazuki Tsuda
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Publication number: 20240260257Abstract: A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.Type: ApplicationFiled: April 25, 2022Publication date: August 1, 2024Inventors: Hitoshi KUNITAKE, Yuki ITO
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Patent number: 12041762Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.Type: GrantFiled: May 19, 2020Date of Patent: July 16, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuaki Ohshima, Hitoshi Kunitake, Takahiro Fukutome
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Patent number: 12009432Abstract: A transistor whose characteristic degradation due to stray light is small is provided. The transistor includes a first insulator, a second insulator over the first insulator, a metal oxide over the second insulator, a first and a second conductor over the metal oxide, a third insulator over the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor, a fourth insulator over the metal oxide, a fifth insulator over the fourth insulator, and a third conductor over the fifth insulator. The third insulator has an opening to overlap with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor are positioned in the opening. The metal oxide has a bandgap greater than or equal to 3.3 eV. The transistor has Vsh higher than or equal to ?0.3 V.Type: GrantFiled: February 24, 2022Date of Patent: June 11, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hitoshi Kunitake, Yasuhiro Jinbo, Naoki Okuno, Masahiro Takahashi, Tomonori Nakayama
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Patent number: 11985827Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.Type: GrantFiled: January 6, 2021Date of Patent: May 14, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiromichi Godo, Hitoshi Kunitake, Kazuki Tsuda
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Publication number: 20240154040Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Eri SATO, Tatsuya Onuki, Yuto Yakubo, Hitoshi Kunitake
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Publication number: 20240147708Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell and a first memory cell layer including a second substrate and a first element layer including the first memory cell. The first memory cell includes a first transistor and a first capacitor. The first transistor includes a semiconductor layer including a metal oxide in its channel formation region. The first memory cell layer is provided to be stacked over the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The second substrate includes a circuit for performing writing of data to or reading of data from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other through a first through electrode provided in the second substrate and the first element layer.Type: ApplicationFiled: April 26, 2022Publication date: May 2, 2024Inventors: Takanori MATSUZAKI, Yuki OKAMOTO, Tatsuya ONUKI, Hitoshi KUNITAKE
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Patent number: 11963343Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.Type: GrantFiled: August 22, 2022Date of Patent: April 16, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hitoshi Kunitake, Ryunosuke Honda, Tomoaki Atsumi
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Patent number: 11948945Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region.Type: GrantFiled: May 18, 2020Date of Patent: April 2, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuto Yakubo, Hitoshi Kunitake, Takayuki Ikeda
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Publication number: 20240105855Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hitoshi KUNITAKE
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Patent number: 11935961Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.Type: GrantFiled: October 15, 2019Date of Patent: March 19, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Eri Sato, Tatsuya Onuki, Yuto Yakubo, Hitoshi Kunitake
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Patent number: 11901822Abstract: A semiconductor device in which an increase in circuit area is inhibited is provided. The semiconductor device includes a first circuit layer and a second circuit layer over the first circuit layer; the first circuit layer includes a first transistor; the second circuit layer includes a second transistor; a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor; a source and a drain of the second transistor are electrically connected to the other of the source and the drain of the first transistor; and a semiconductor layer of the second transistor contains a metal oxide.Type: GrantFiled: May 19, 2020Date of Patent: February 13, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuto Yakubo, Hitoshi Kunitake, Takayuki Ikeda
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Patent number: 11894040Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes a plurality of constant current circuits each given a digital signal. The constant current circuits each include a first transistor to a third transistor. The first transistor has a function of making a first current corresponding to set analog potential flow therethrough. The second transistor has a function of controlling the first current flowing between a source and a drain of the first transistor, in response to the digital signal. The third transistor has a function of holding the analog potential supplied to a gate of the first transistor, by being turned off. The first transistor to the third transistor each include a semiconductor layer including an oxide semiconductor in a channel formation region.Type: GrantFiled: June 30, 2020Date of Patent: February 6, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takayuki Ikeda, Hitoshi Kunitake
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Publication number: 20240038529Abstract: A method for depositing a metal oxide is provided. The deposition method of a metal oxide includes a first step of introducing a first precursor into a first chamber, a second step of introducing a second precursor into the first chamber, a third step of introducing a third precursor into the first chamber, a fourth step of introducing an oxidizer in a plasma state into the first chamber after each of the first step, the second step, and the third step, and a fifth step of performing microwave treatment. Performing each of the first to fourth steps one or more times is regarded as one cycle, and the fifth step is performed in a second chamber after the one cycle is repeated a plurality of times.Type: ApplicationFiled: August 17, 2021Publication date: February 1, 2024Inventors: Shunpei YAMAZAKI, Yuji EGI, Yasuhiro JINBO, Hitoshi KUNITAKE
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Patent number: 11876138Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.Type: GrantFiled: October 15, 2019Date of Patent: January 16, 2024Inventors: Eri Sato, Tatsuya Onuki, Yuto Yakubo, Hitoshi Kunitake
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Publication number: 20230411521Abstract: A transistor having a large S value or a semiconductor device performing calculation utilizing a transistor operation in a subthreshold region is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a gate electrode including a region overlapping with the oxide semiconductor layer with an insulating layer therebetween, and a first conductive layer including a region overlapping with the oxide semiconductor layer with a ferroelectric layer therebetween. In particular, the ferroelectric layer includes a crystal having a crystal structure exhibiting ferroelectricity.Type: ApplicationFiled: November 9, 2021Publication date: December 21, 2023Inventors: Yuki ITO, Hitoshi KUNITAKE, Kazuki TANEMURA
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Patent number: 11848697Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.Type: GrantFiled: June 3, 2020Date of Patent: December 19, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takayuki Ikeda, Hitoshi Kunitake
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Patent number: 11843059Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.Type: GrantFiled: April 4, 2022Date of Patent: December 12, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hajime Kimura, Hitoshi Kunitake