Abstract: Provided is a semiconductor device capable of retaining data for a long time. The semiconductor device includes a cell provided with a capacitor, a first transistor, and a second transistor; the capacitor includes a first electrode, a second electrode, and a ferroelectric layer; the ferroelectric layer is provided between the first electrode and the second electrode and polarization reversal occurs by application of a first saturated polarization voltage or a second saturated polarization voltage whose polarity is different from that of the first saturated polarization voltage; and the first electrode, one of a source and a drain of the first transistor, and a gate of the second transistor are electrically connected to one another. In a first period, the first saturated polarization voltage is applied to the ferroelectric layer.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening.

Abstract: To provide a mixer and a semiconductor device which each have a small circuit area and each of which operation capability is inhibited from being decreased due to heat. The mixer includes a differential portion, a current source, a first load, an input terminal, and a first output terminal; the differential portion includes a first and a second transistor; and each of the first and the second transistors includes a metal oxide in a channel formation region. A first terminal of each of the first and the second transistors is electrically connected to the input terminal and a current source and a second terminal of the first transistor is electrically connected to a first terminal of the first load and the first output terminal.

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Abstract: A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Abstract: A semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof are provided. A semiconductor device includes a metal oxide, a first conductor and a second conductor over the metal oxide, a first insulator positioned over the metal oxide and between the first conductor and the second conductor, a second insulator over the first insulator, a third insulator over the second insulator, a third conductor over the third insulator, a fourth insulator positioned between the first conductor and the first insulator, and a fifth insulator positioned between the second conductor and the first insulator. The first insulator is in contact with the top surface and the side surface of the metal oxide, and oxygen is less likely to pass through the first insulator than the second insulator. The first conductor, the second conductor, the fourth insulator, and the fifth insulator contain the same metal element.

Abstract: A semiconductor device with a high on-state current is provided. A transistor included in the semiconductor device includes a first insulator; a first semiconductor layer over the first insulator; a second semiconductor layer including a channel formation region over the first semiconductor layer; a first conductor and a second conductor over the second semiconductor layer; a second insulator over the second semiconductor layer and between the first conductor and the second conductor; and a third conductor over the second insulator. In a cross-sectional view in a channel width direction of the transistor, the third conductor covers a side surface and a top surface of the second semiconductor layer. The second semiconductor layer has a higher permittivity than the first semiconductor layer.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor including a first oxide, a second transistor including a second oxide, and a third oxide. The first oxide includes a channel formation region of the first transistor. The second oxide includes a channel formation region of the second transistor. The third oxide contains the same material as the first oxide and the second oxide. The third oxide is separated from the first oxide and the second oxide. In a top view, the third oxide is positioned between the first oxide and the second oxide. The third oxide is placed in the same layer as the first oxide and the second oxide.

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

Abstract: A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer.

Abstract: Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.

Abstract: A semiconductor device including an oxide semiconductor layer which is formed over a substrate and includes indium is provided. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a formation surface of the oxide semiconductor layer to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the formation surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formation surface are observed in each of the first region, the second region, and the third region.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a first metal oxide, a first conductor, a second conductor, and a third conductor. The first metal oxide includes a first depressed portion, a second depressed portion, and a third depressed portion positioned between the first depressed portion and the second depressed portion. The first conductor is provided to fill the first depressed portion, and the second conductor is provided to fill the second depressed portion. A top surface of the first conductor and a top surface of the second conductor are level with or substantially level with a top surface of the first metal oxide. The first insulator is provided inside the third depressed portion. The third conductor is provided over the first insulator and includes a region overlapping with the first metal oxide with the first insulator therebetween.

Abstract: A transistor that can be miniaturized is provided. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. Over the first conductive layer including a depressed portion, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer which include a first opening portion overlapping with the depressed portion are provided in this order. The third insulating layer is in contact with at least the side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the depressed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is on an inner side of the oxide semiconductor layer in the first opening portion.

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

Abstract: A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a first electrode, a transistor including a back gate, a capacitor including a pair of electrodes, and a first insulator that can have ferroelectricity between the back gate of the transistor and a semiconductor. The first insulator overlaps with the semiconductor with a second insulator therebetween. One of a source electrode and a drain of the transistor is electrically connected to the first electrode. The other of the source and the drain of the transistor is electrically connected to one electrode of the pair of electrodes. The pair of electrodes are each in contact with the first insulator and include a region where the pair of electrodes overlap with each other with the first insulator therebetween. As the first insulator, a ferroelectric is used.

Abstract: A memory element with a novel structure is provided. The memory element includes a stack of a first electrode, a first insulating layer, a semiconductor layer, a second insulating layer, and a second electrode. The first electrode, the first insulating layer, the semiconductor layer, the second insulating layer, and the second electrode include a region where they overlap with each other. An oxide semiconductor, which is a kind of a metal oxide, is used for the semiconductor layer. For the first insulating layer, a material having anti-ferroelectricity is used.