Abstract: A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.

Abstract: A material having favorable ferroelectricity is provided. An embodiment of the present invention is a metal oxide film including a first layer and a second layer. The first layer contains first oxygen and hafnium, and the second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other with the first oxygen positioned therebetween, and the second oxygen is bonded to the zirconium.

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.

Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor, a connection portion, a first insulator, a second insulator, and a first wiring. The connection portion includes a first electrode and a second electrode. The first transistor includes the second electrode, a third electrode, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator includes a first opening reaching the first wiring. The first electrode is in contact with a side surface of the first opening and the top surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator includes a second opening reaching the second electrode. The third electrode is provided over the second insulator. The first semiconductor is in contact with the third electrode, a side surface of the second insulator in the second opening, and the top surface of the second electrode.

Abstract: A memory device that can be miniaturized or highly integrated can be provided. The memory device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor and a transistor over the capacitor. The capacitor includes a second conductor, a third insulator over the second conductor, and a third conductor over the third insulator. Part of the second conductor, part of the third insulator, and part of the third conductor are placed in an opening portion formed in the first insulator. The transistor includes the third conductor, a fourth conductor over the second insulator, an oxide semiconductor, a fourth insulator over the oxide semiconductor, and a fifth conductor over the fourth insulator. Part of the oxide semiconductor is placed in an opening portion formed in the second insulator and the fourth conductor.

Abstract: A memory device having large memory capacity is provided. A highly reliable memory device is provided. A semiconductor device includes a first conductive layer extending in a first direction, a structure body extending in a second direction intersecting with the first direction, a first insulating layer, and a second insulating layer. The structure body includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. In an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer.

Abstract: A memory device comprising a memory cell over a first transistor including silicon in a semiconductor layer is provided. The memory cell includes a capacitor and a second transistor over the capacitor. The capacitor includes a first conductor, a first insulator, and a second conductor that are stacked in this order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor functioning as the other of the source and the drain of the second transistor is located over the second insulator. An opening reaching the second conductor is provided in the second insulator and the third conductor. An oxide semiconductor, a third insulator, and a fourth conductor are stacked in this order to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.

Abstract: A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.

Abstract: A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.

Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a second insulator over the first insulator; a third insulator over the second insulator; an oxide semiconductor placed over the second insulator and covering the third insulator; a first conductor and a second conductor over the oxide semiconductor; a fourth insulator placed over the first conductor and the second conductor; a fifth insulator placed over the oxide semiconductor; and a third conductor placed over the fifth insulator. The second insulator and the fourth insulator include an opening reaching the oxide semiconductor and reaching the first insulator in a region not overlapping with the oxide semiconductor, in a region between the first conductor and the second conductor. The fifth insulator and the third conductor are placed in the opening.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.

Abstract: A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.

Abstract: Included are a first insulator over a substrate, an oxide semiconductor covering at least part of the first insulator, a first conductor and a second conductor over the oxide semiconductor, a second insulator over the first conductor, a third insulator over the second conductor, a third conductor over the second insulator, a fourth conductor over the third insulator, a fourth insulator placed over the third conductor and the fourth conductor and having a first opening overlapping with an area between the first conductor, the second insulator, and the third conductor and the second conductor, the third insulator, and the fourth conductor, a fifth insulator placed in the first opening, a fifth conductor placed over the fifth insulator, a sixth conductor placed in a second opening formed in the fourth insulator and being in contact with a top surface of the third conductor, and a seventh conductor placed in a third opening formed in the fourth insulator, the third insulator, and the fourth conductor and being in

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor over the first transistor. The first transistor includes a first oxide semiconductor over a substrate, a first conductor and a second conductor that are over the first oxide semiconductor and apart from each other, a first insulator that is positioned over the first conductor and the second conductor and includes an opening overlapping with a region between the first conductor and the second conductor, a second insulator positioned in the opening of the first insulator and over the first oxide semiconductor, and a third conductor positioned in the opening and over the second insulator.

Abstract: A memory device that can be miniaturized or highly integrated is provided.

Abstract: A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.