Abstract: A semiconductor device with a novel structure is provided. First to third element layers are included. The second element layer is stacked over the first element layer. The third element layer is stacked over the second element layer. A first storage portion is provided in the second element layer. A second storage portion is provided in the third element layer. The first element layer includes a first sense amplifier circuit portion electrically connected to the first storage portion, and a second sense amplifier circuit portion electrically connected to the second storage portion. The first sense amplifier circuit portion and the second sense amplifier circuit portion each include a first transistor including a first semiconductor layer including silicon in a channel formation region. The first storage portion includes a second transistor including a second semiconductor layer including an oxide semiconductor in a channel formation region.

Abstract: A transistor with small parasitic capacitance is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first insulating layer and the second conductive layer have an opening reaching the first conductive layer. In the opening, the oxide semiconductor layer is in contact with at least the top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. The second insulating layer is positioned over the oxide semiconductor layer in the opening.

Abstract: A semiconductor device that includes different kinds of memory devices in the same chip is provided. Data transfer speed between two memory devices is improved. The semiconductor device includes a first layer, a second layer, and a third layer. The first layer includes a first storage device where a plurality of nonvolatile first storage elements are stacked in a thickness direction of the first layer. The second layer includes a second storage device that includes a plurality of second storage elements each including a transistor including an oxide semiconductor. The third layer includes a first driver circuit controlling operation of the first storage device and a second driver circuit controlling operation of the second storage device. The first layer, the second layer, and the third layer include a portion where they overlap each other.

Abstract: A semiconductor device comprising a first layer including a processing portion and a sense amplifier and a second layer including a memory cell is provided. The memory cell is included in a memory device that is used as a cache memory or a main memory in the processing portion. The sense amplifier has a function of reading data retained in the memory cell, and the memory cell includes a transistor and a capacitor. In particular, the transistor is a vertical transistor whose channel formation region is included in a first opening of a first insulating layer. The capacitor includes a first capacitor region in a second opening of a second insulating layer and a second capacitor region in a region overlapping with a top surface of the second insulating layer. The first opening includes a region overlapping with at least part of the second capacitor region.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided, which includes a memory device, a sense amplifier, and a processing portion. The sense amplifier and the processing portion are placed on a first layer, and the memory device is placed on a second layer stacked over the first layer. The memory device includes first and second transistors and a capacitor, the second transistor and the capacitor are each provided over the first transistor to overlap therewith, and the second transistor is positioned diagonally above the first transistor. A source electrode and a drain electrode of each of the first and second transistors are provided at different levels with respect to a substrate surface to overlap with each other. A gate electrode of the first transistor has both a function of one of the source electrode and the drain electrode of the second transistor and a function of one electrode of the capacitor.

Abstract: A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.

Abstract: A metal oxide film having high carrier mobility is provided. In the metal oxide film, a sum of a content percentage of indium and a content percentage of zinc is greater than or equal to 95%. The metal oxide film includes a crystal. The crystal includes a layered crystal structure. In the crystal, the ratio of the number of zinc atoms to the number of indium atoms is greater than 0 and less than 1.5. The electron effective mass in the crystal is smaller than the electron effective mass in an indium oxide having a cubic crystal structure. The metal oxide film may include tin, and the content percentage of tin is higher than or equal to 0.1% and lower than or equal to 3%.

Abstract: A semiconductor device with a reduced number of steps is provided. The semiconductor device includes a first transistor and a second transistor in a memory cell. As each of the two transistors, a vertical transistor including a channel formation region on a side surface of an opening portion formed in an insulating layer and having a small occupied area is used. Some unevenness due to the components of the first transistor is allowed, and the second transistor is placed obliquely above the first transistor not to cause a defect due to the unevenness, whereby the number of steps in a planarization process or the like is reduced.

Abstract: A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.

Abstract: A transistor having a large S value or a semiconductor device performing calculation utilizing a transistor operation in a subthreshold region is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a gate electrode including a region overlapping with the oxide semiconductor layer with an insulating layer therebetween, and a first conductive layer including a region overlapping with the oxide semiconductor layer with a ferroelectric layer therebetween. In particular, the ferroelectric layer includes a crystal having a crystal structure exhibiting ferroelectricity.

Abstract: A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element and an input terminal of the second FTJ element. In data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with the data. In data reading, voltage with which the polarization does not change is applied between the output terminal of the first FTJ element and the input terminal of the second FTJ element. At this time, the first transistor is turned on, whereby a differential current between current flowing through the first FTJ element and current flowing through the second FTJ element flows through the first transistor.

Abstract: A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.

Abstract: A material having favorable ferroelectricity is provided. An embodiment of the present invention is a metal oxide film including a first layer and a second layer. The first layer contains first oxygen and hafnium, and the second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other with the first oxygen positioned therebetween, and the second oxygen is bonded to the zirconium.

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.

Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor, a connection portion, a first insulator, a second insulator, and a first wiring. The connection portion includes a first electrode and a second electrode. The first transistor includes the second electrode, a third electrode, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator includes a first opening reaching the first wiring. The first electrode is in contact with a side surface of the first opening and the top surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator includes a second opening reaching the second electrode. The third electrode is provided over the second insulator. The first semiconductor is in contact with the third electrode, a side surface of the second insulator in the second opening, and the top surface of the second electrode.

Abstract: A memory device that can be miniaturized or highly integrated can be provided. The memory device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor and a transistor over the capacitor. The capacitor includes a second conductor, a third insulator over the second conductor, and a third conductor over the third insulator. Part of the second conductor, part of the third insulator, and part of the third conductor are placed in an opening portion formed in the first insulator. The transistor includes the third conductor, a fourth conductor over the second insulator, an oxide semiconductor, a fourth insulator over the oxide semiconductor, and a fifth conductor over the fourth insulator. Part of the oxide semiconductor is placed in an opening portion formed in the second insulator and the fourth conductor.

Abstract: A memory device having large memory capacity is provided. A highly reliable memory device is provided. A semiconductor device includes a first conductive layer extending in a first direction, a structure body extending in a second direction intersecting with the first direction, a first insulating layer, and a second insulating layer. The structure body includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. In an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer.

Abstract: A memory device comprising a memory cell over a first transistor including silicon in a semiconductor layer is provided. The memory cell includes a capacitor and a second transistor over the capacitor. The capacitor includes a first conductor, a first insulator, and a second conductor that are stacked in this order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor functioning as the other of the source and the drain of the second transistor is located over the second insulator. An opening reaching the second conductor is provided in the second insulator and the third conductor. An oxide semiconductor, a third insulator, and a fourth conductor are stacked in this order to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.