Abstract: A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

Abstract: A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.

Abstract: A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

Abstract: A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

Abstract: A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

Abstract: A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

Abstract: A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.

Abstract: A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mode setting cycle. In the normal mode, setting of addresses is performed irrespective of a clock signal. In the synchronous mode, an edge of the clock signal determines the timing of operation.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

Abstract: A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mode setting cycle. In the normal mode, setting of addresses is performed irrespective of a clock signal. In the synchronous mode, an edge of the clock signal determines the timing of operation.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

Abstract: A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mode setting cycle. In the normal mode, setting of addresses is performed irrespective of a clock signal. In the synchronous mode, an edge of the clock signal determines the timing of operation.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

Abstract: A signal receiving system includes a plurality of first receivers and at least one second receiver driven based on a sensing result output from the first receivers, the first receivers driven at predetermined time intervals and sensing a time-based change in a first signal. Each of the first receivers holds the first signal with a predetermined time difference and thereby converts the time-based change in the first signal into positional information. The signal receiving system may also include a clock generation section that generates clock signals that are different in phase. The signal receiving system is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver that receives states of the strobe signals at the respective times and second multiphase clocks, which lag the first multiphase clocks by a predetermined length of time.

Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S·N·F.

Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S•N•F.

Abstract: A semiconductor device includes a memory cell array, a control section and latency setting circuit. The control section configured to receive a clock signal and a first control signal, and configured to output a plurality of the data in synchronism with the clock signal after the first control signal is asserted, output of the data beginning a number of clock cycles (latency N) of the clock signal (latency N being a positive integer ≧2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output. The latency setting circuit sets the latency N. The latency setting circuit includes at least one switch which permanently fixes a latency.

Abstract: A dynamic random access memory device includes a bit line, a memory cell coupled to the bit line, and a word line coupled to the memory cell. A read activation time between receiving a read command for a read operation in order to read data: from the memory cell and activating the word-line-may be different from a write activation time between receiving a write command for a write operation in order to write data to the memory cell and activating the word line.

Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S≧N≧F.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.