Patents by Inventor Hitoshi Miwa
Hitoshi Miwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030016576Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: ApplicationFiled: August 20, 2002Publication date: January 23, 2003Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6459614Abstract: At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.Type: GrantFiled: December 19, 2001Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Publication number: 20020136056Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: March 13, 2002Publication date: September 26, 2002Applicant: Hitachi, Ltd.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 6452838Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: November 27, 2001Date of Patent: September 17, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20020071309Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: ApplicationFiled: December 19, 2001Publication date: June 13, 2002Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6392932Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: November 17, 2000Date of Patent: May 21, 2002Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20020054511Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: November 27, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 6385092Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: September 25, 2001Date of Patent: May 7, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 6366495Abstract: At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.Type: GrantFiled: March 27, 2001Date of Patent: April 2, 2002Assignee: Hitachi, Ltd.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Publication number: 20020034099Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: September 25, 2001Publication date: March 21, 2002Applicant: Hitaci, Ltd.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20010028576Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: ApplicationFiled: March 27, 2001Publication date: October 11, 2001Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6256230Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: GrantFiled: May 31, 2000Date of Patent: July 3, 2001Assignee: Hitachi, Ltd.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6243313Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.Type: GrantFiled: July 18, 2000Date of Patent: June 5, 2001Assignee: Hitachi, Ltd.Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima
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Patent number: 6226212Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data reading time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.Type: GrantFiled: March 31, 1998Date of Patent: May 1, 2001Assignee: Hitachi, Ltd.Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima
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Patent number: 6226198Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: GrantFiled: December 27, 1999Date of Patent: May 1, 2001Assignee: Hitachi, Ltd.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6166949Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state corresponding to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: GrantFiled: June 29, 1998Date of Patent: December 26, 2000Assignee: Hitachi, Ltd.Inventor: Hitoshi Miwa
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Patent number: 6157573Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: December 21, 1999Date of Patent: December 5, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 6121681Abstract: A resin-encapsulated semiconductor package and a packaging structure, make it possible to provide for a high density mounting arrangement. Specifically, outer leads protrude from the two long sides of a rectangular package. The inner leads in the package, connected to the outer leads protruding from one long side, are connected through wires to the bonding pads of a semiconductor chip encapsulated in the package, whereas the inner leads in the package, connected to the outer leads protruding from the other long side, are in an electrically floating state in the package. The semiconductor packages are arranged in a direction on a card-shaped mounting board, and the opposed outer leads of adjoining semiconductor packages are electrically connected by wiring on the mounting board. The wirings are laid below the semiconductor packages so that they extend generally linearly.Type: GrantFiled: May 14, 1997Date of Patent: September 19, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shigeru Tanaka, Yasuhiro Nakamura, Hitoshi Miwa, Kazuyuki Miyazawa
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Patent number: 6111790Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state corresponding to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.Type: GrantFiled: April 6, 1999Date of Patent: August 29, 2000Assignee: Hitachi, Ltd.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 6079390Abstract: In an initial opening degree setting mechanism which keeps an initial opening degree of a throttle valve (24) larger than that of a fully closed position thereof when no current is supplied to a motor (12) for driving a throttle shaft (18) for the throttle valve (24), a throttle lever (3) and a sleeve (45) are inserted into the throttle shaft (18) and secured thereto and a sleeve (42) integrated with a return lever (2) is fitted over the sleeve (45) so as to permit a relative rotational mevement with respect to the sleeve (45). The sleeve (42) is urged by a return spring (4) in the direction of closing the throttle valve (24) upto the position of the initial opening degree. With the urging force the return lever (2) is placed to be engageable with the throttle lever (3).Type: GrantFiled: October 12, 1999Date of Patent: June 27, 2000Assignee: Hitachi, Ltd.Inventors: Yoshikatsu Hashimoto, Shigeo Tamaki, Shigeru Tokumoto, Hitoshi Miwa