Patents by Inventor Hitoshi Miwa
Hitoshi Miwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8004905Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: March 18, 2010Date of Patent: August 23, 2011Assignee: Renesas Electronics CorporationInventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20110084758Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.Type: ApplicationFiled: October 7, 2010Publication date: April 14, 2011Applicant: Elpida Memory, Inc.Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
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Publication number: 20100182847Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: March 18, 2010Publication date: July 22, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 7697345Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: June 25, 2008Date of Patent: April 13, 2010Assignee: Renesas Technology Corp.Inventors: Tetsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20100020615Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: ApplicationFiled: May 4, 2009Publication date: January 28, 2010Inventors: Hitoshi MIWA, Hiroaki Kotani
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Patent number: 7542339Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: August 20, 2007Date of Patent: June 2, 2009Assignee: Solid State Storage Solutions, LLCInventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7489030Abstract: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.Type: GrantFiled: December 8, 2006Date of Patent: February 10, 2009Assignee: Elpida Memory, Inc.Inventors: Kayoko Shibata, Hiroaki Ikeda, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
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Publication number: 20090003085Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: June 25, 2008Publication date: January 1, 2009Inventors: Tatsuya ISHII, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 7405979Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: September 7, 2007Date of Patent: July 29, 2008Assignee: Renesas Technology Corp.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Patent number: 7327604Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: November 17, 2006Date of Patent: February 5, 2008Assignee: Renesas Technology CorporationInventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7324375Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: May 8, 2006Date of Patent: January 29, 2008Assignee: Solid State Storage Solutions, LLCInventors: Hitoshi Miwa, Hiroaki Kotani
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Publication number: 20080008009Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: September 7, 2007Publication date: January 10, 2008Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20070291538Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: ApplicationFiled: August 20, 2007Publication date: December 20, 2007Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7286397Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: March 25, 2005Date of Patent: October 23, 2007Assignee: Renesas Technology CorporationInventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7283399Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: GrantFiled: August 3, 2006Date of Patent: October 16, 2007Assignee: Renesas Technology Corp.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20070132085Abstract: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.Type: ApplicationFiled: December 8, 2006Publication date: June 14, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Kayoko Shibata, Hiroaki Ikeda, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
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Publication number: 20070126105Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.Type: ApplicationFiled: December 6, 2006Publication date: June 7, 2007Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
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Publication number: 20070064483Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: ApplicationFiled: November 17, 2006Publication date: March 22, 2007Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7193894Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: March 29, 2004Date of Patent: March 20, 2007Assignee: Renesas Technology Corp.Inventors: Hitoshi Miwa, Hiroaki Kotani
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Patent number: 7161830Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.Type: GrantFiled: December 30, 2004Date of Patent: January 9, 2007Assignee: Renesas Technology Corp.Inventors: Hitoshi Miwa, Hiroaki Kotani