Patents by Inventor Hitoshi Ninomiya

Hitoshi Ninomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190283548
    Abstract: A humidifying device includes a casing that defines a first air passage that guides air to an adsorbent module accommodation portion accommodating an adsorbent module including an adsorbent, and a second air passage through which the air flowing out of the adsorbent module accommodation portion flows. The humidifying device includes a peltier device that has a heat absorbing side and a heat generating side generating heat due to heat transfer from the heat absorbing side. The peltier device is housed in the casing such that the heat generating side is located in the first air passage and the heat absorbing side is located in the second air passage.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Miyuki SAITO, Manabu MAEDA, Hitoshi NINOMIYA, Yusuke KOMATSUBARA, Daichi TSUBOKURA
  • Patent number: 10272745
    Abstract: A humidifying device for a vehicle has a humidity detection part, a blower, a non-water-supply humidifier, and a controller. The humidity detection part detects a humidity in a vehicle compartment. The blower draws, as an intake air, an inside air in the vehicle compartment and an outside air outside the vehicle compartment at a specified ratio and blows the intake air toward the vehicle compartment. The non-water-supply humidifier collects water included in the inside air and supplies a humidified air, which is humidified using the water, toward a specified area in the vehicle compartment. The controller sets the specified ratio between the inside air and the outside air and controls an operation of the non-water-supply humidifier. The controller controls the blower to draw at least the inside air, when the non-water-supply humidifier is operated, and when a humidity in the vehicle compartment is lower than a specified humidity.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: April 30, 2019
    Assignee: DENSO CORPORATION
    Inventors: Takuya Kataoka, Manabu Maeda, Hitoshi Ninomiya, Yusuke Komatsubara
  • Publication number: 20170282690
    Abstract: A humidifying device for a vehicle has a humidity detection part, a blower, a non-water-supply humidifier, and a controller. The humidity detection part detects a humidity in a vehicle compartment. The blower draws, as an intake air, an inside air in the vehicle compartment and an outside air outside the vehicle compartment at a specified ratio and blows the intake air toward the vehicle compartment. The non-water-supply humidifier collects water included in the inside air and supplies a humidified air, which is humidified using the water, toward a specified area in the vehicle compartment. The controller sets the specified ratio between the inside air and the outside air and controls an operation of the non-water-supply humidifier. The controller controls the blower to draw at least the inside air, when the non-water-supply humidifier is operated, and when a humidity in the vehicle compartment is lower than a specified humidity.
    Type: Application
    Filed: September 1, 2015
    Publication date: October 5, 2017
    Inventors: Takuya KATAOKA, Manabu MAEDA, Hitoshi NINOMIYA, Yusuke KOMATSUBARA
  • Patent number: 8035158
    Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Patent number: 7919374
    Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: April 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Patent number: 7851308
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Patent number: 7829417
    Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura, Yoshiya Kawashima
  • Patent number: 7825466
    Abstract: The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20100100266
    Abstract: A thermal management system for a vehicle includes a switching power supply device, an electronic member configured to output an electrical power adjusted by the switching power supply device, and a control device configured to control operation of the switching power supply device. When the control device receives a heating request from at least one of devices that include a drive device used for driving the vehicle and an air conditioning device used for performing an air conditioning in a vehicle compartment, the control device causes the switching power supply device to be operated in a heat increasing operation in which heat generated from the electronic member is increased more than that in a general operation state, and supplies the generated heat to the at least one of the drive device and the air conditioning device.
    Type: Application
    Filed: October 16, 2009
    Publication date: April 22, 2010
    Applicant: DENSO CORPORATION
    Inventors: Takeshi Yoshinori, Yasumitsu Oomi, Hitoshi Ninomiya, Masamichi Makihara, Kouji Mori, Yoshimitsu Inoue
  • Patent number: 7696061
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Publication number: 20090275180
    Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 5, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Hitoshi NINOMIYA, Yoshinao Miura
  • Patent number: 7538388
    Abstract: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: May 26, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20080298291
    Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.
    Type: Application
    Filed: April 28, 2008
    Publication date: December 4, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshinao MIURA, Hitoshi Ninomiya
  • Publication number: 20080299726
    Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi NINOMIYA, Yoshinao MIURA, Yoshiya KAWASHIMA
  • Patent number: 7432134
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: October 7, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20080213960
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer.
    Type: Application
    Filed: September 5, 2007
    Publication date: September 4, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi NINOMIYA
  • Publication number: 20080197381
    Abstract: A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshiya Kawashima, Yoshinao Miura, Hitoshi Ninomiya
  • Publication number: 20080076223
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Application
    Filed: November 21, 2007
    Publication date: March 27, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Patent number: 7335949
    Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 26, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Publication number: 20080032477
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Application
    Filed: September 26, 2007
    Publication date: February 7, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hitoshi Ninomiya