Abstract: A flip-flop arrangement receiving a clock signal and an input data and outputting a logical output in accordance with a logical level of the data. The arrangement includes a master flip-flop for transmitting a change in the logical level of the data to a pair of output ends when the clock signal is at a predetermined logical level; a slave flip-flop for latching the data transmitted via the pair of output ends; an output buffer for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit for driving the output buffer. The drive circuit responds to logical levels of data appearing at the pair of output ends of the master flip-flop and, based on the logical levels, drives the output buffer to determine a logical output to be output from the arrangement, thereby reducing a total propagation delay time and realizing a high speed operation without increasing a power dissipation.

Abstract: The air flow rate of a fan driven by a motor controlled by an adjustable speed control equipment is automatically controlled by stopping the adjustable speed control equipment in response to a fault signal therefrom during operation with an inlet vane installed upstream of the fan in fully open state, simultaneously throttling the inlet vane at a preset speed to a degree of opening appropriate for the load by means of a control circuit, and, after a period for reduction of residual voltage of the motor, changing over to operation of the fan by a commercial power supply thereby to shift to control by the degree of opening of the inlet vane.