Patents by Inventor Hitoshi SUGAHARA
Hitoshi SUGAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836906Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.Type: GrantFiled: October 18, 2021Date of Patent: December 5, 2023Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Shinichi Shinoda, Yasutaka Toyoda, Shigetoshi Sakimura, Masayoshi Ishikawa, Hiroyuki Shindo, Hitoshi Sugahara
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Patent number: 11443917Abstract: The present invention relates to an image generation method for an objective for generating an image corresponding to a multi-frame image from image signals obtained by scanning a small number of frames are proposed.Type: GrantFiled: June 3, 2020Date of Patent: September 13, 2022Assignee: Hitachi High-Tech CorporationInventors: Chikako Abe, Hitoshi Sugahara
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Publication number: 20220036116Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Inventors: Shinichi SHINODA, Yasutaka TOYODA, Shigetoshi SAKIMURA, Masayoshi ISHIKAWA, Hiroyuki SHINDO, Hitoshi SUGAHARA
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Patent number: 11176405Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.Type: GrantFiled: March 15, 2018Date of Patent: November 16, 2021Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Shinichi Shinoda, Yasutaka Toyoda, Shigetoshi Sakimura, Masayoshi Ishikawa, Hiroyuki Shindo, Hitoshi Sugahara
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Patent number: 10937628Abstract: The purpose of the present invention is to provide a charged particle beam device with which it is possible to identify, to a high degree of accuracy, repeat patterns generated by a multiple exposure method such as SADP or SAQP.Type: GrantFiled: January 27, 2017Date of Patent: March 2, 2021Assignee: Hitachi High-Tech CorporationInventors: Chikako Abe, Hitoshi Sugahara
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Publication number: 20210043418Abstract: The present invention relates to an image generation method for an objective for generating an image corresponding to a multi-frame image from image signals obtained by scanning a small number of frames are proposed.Type: ApplicationFiled: June 3, 2020Publication date: February 11, 2021Inventors: Chikako ABE, Hitoshi SUGAHARA
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Publication number: 20200134355Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.Type: ApplicationFiled: March 15, 2018Publication date: April 30, 2020Inventors: Shinichi SHINODA, Yasutaka TOYODA, Shigetoshi SAKIMURA, Masayoshi ISHIKAWA, Hiroyuki SHINDO, Hitoshi SUGAHARA
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Patent number: 10558127Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.Type: GrantFiled: December 18, 2015Date of Patent: February 11, 2020Assignee: Hitachi High-Technologies CorporationInventors: Shinichi Shinoda, Yasutaka Toyoda, Hiroyuki Ushiba, Hitoshi Sugahara
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Publication number: 20190362938Abstract: The purpose of the present invention is to provide a charged particle beam device with which it is possible to identify, to a high degree of accuracy, repeat patterns generated by a multiple exposure method such as SADP or SAQP.Type: ApplicationFiled: January 27, 2017Publication date: November 28, 2019Inventors: Chikako ABE, Hitoshi SUGAHARA
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Patent number: 10445875Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.Type: GrantFiled: April 27, 2018Date of Patent: October 15, 2019Assignee: Hitachi High-Technologies CorporationInventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
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Patent number: 10190875Abstract: The purpose of the present invention is to provide a pattern measurement condition setting device which appropriately sets a measurement condition for finding out an appropriate exposure condition.Type: GrantFiled: June 17, 2015Date of Patent: January 29, 2019Assignee: Hitachi High-Technologies CorporationInventors: Shinichi Shinoda, Yasutaka Toyoda, Hiroyuki Ushiba, Hitoshi Sugahara
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Publication number: 20180247400Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.Type: ApplicationFiled: April 27, 2018Publication date: August 30, 2018Inventors: Yasutaka TOYODA, Norio HASEGAWA, Takeshi KATO, Hitoshi SUGAHARA, Yutaka HOJO, Daisuke HIBINO, Hiroyuki SHINDO
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Patent number: 9990708Abstract: An object of the present invention is to provide a pattern-measuring apparatus and a semiconductor-measuring system which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In the present invention for attaining the object described above, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.Type: GrantFiled: February 5, 2014Date of Patent: June 5, 2018Assignee: Hitachi High-Technologies CorporationInventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
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Publication number: 20170336717Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.Type: ApplicationFiled: December 18, 2015Publication date: November 23, 2017Applicant: Hitachi High-Technologies CorporationInventors: Shinichi SHINODA, Yasutaka TOYODA, Hiroyuki USHIBA, Hitoshi SUGAHARA
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Publication number: 20170160082Abstract: The purpose of the present invention is to provide a pattern measurement condition setting device which appropriately sets a measurement condition for finding out an appropriate exposure condition.Type: ApplicationFiled: June 17, 2015Publication date: June 8, 2017Inventors: Shinichi SHINODA, Yasutaka TOYODA, Hiroyuki USHIBA, Hitoshi SUGAHARA
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Publication number: 20160005157Abstract: An object of the present invention is to provide a pattern-measuring apparatus and a semiconductor-measuring system which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In the present invention for attaining the object described above, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.Type: ApplicationFiled: February 5, 2014Publication date: January 7, 2016Inventors: Yasutaka TOYODA, Norio HASEGAWA, Takeshi KATO, Hitoshi SUGAHARA, Yutaka HOJO, Daisuke HIBINO, Hiroyuki SHINDO
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Patent number: 8959461Abstract: A pattern measurement device includes: a storage section storing mask edge data of a circuit pattern and image data obtained by imaging the circuit pattern; an SEM contour extracting section receiving the image data, SEM contour of the circuit pattern, and cause an exposure simulator to generate estimated SEM contour data of an estimated SEM contour on the basis of the mask edge data and SEM contour data of the extracted SEM contour; a shape classifying section receiving the mask edge data, the SEM contour data, and the estimated contour data to classify the SEM contour data and the estimated SEM contour data into a one-dimensionally shaped contour and a two-dimensionally shaped contour; and an SEM contour sampling section receiving the SEM contour data and the estimated SEM contour data to sample the SEM contour data on the basis of types of the one-dimensionally and two-dimensionally shaped contours.Type: GrantFiled: March 23, 2012Date of Patent: February 17, 2015Assignee: Hitachi High-Technologies CorporationInventors: Takuma Shibahara, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
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Patent number: 8942464Abstract: The present invention provides a pattern measuring apparatus (600) that: acquires the image contour of a circuit pattern formed by transferring design data; classifies the acquired image contour into shape structures; calculates normal vectors for each shape structure; maps the shape structures to the image contour; uses at least one normal direction for each shape structure to stabilize the normal directions to the image contour; and uses the normal vectors for each shape structure to determine the position of a SEM contour.Type: GrantFiled: March 28, 2011Date of Patent: January 27, 2015Assignee: Hitachi High-Technologies CorporationInventors: Takuma Shibahara, Tsuyoshi Minakawa, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
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Publication number: 20140224986Abstract: A pattern measurement device includes: a storage section storing mask edge data of a circuit pattern and image data obtained by imaging the circuit pattern; an SEM contour extracting section receiving the image data, SEM contour of the circuit pattern, and cause an exposure simulator to generate estimated SEM contour data of an estimated SEM contour on the basis of the mask edge data and SEM contour data of the extracted SEM contour; a shape classifying section receiving the mask edge data, the SEM contour data, and the estimated contour data to classify the SEM contour data and the estimated SEM contour data into a one-dimensionally shaped contour and a two-dimensionally shaped contour; and an SEM contour sampling section receiving the SEM contour data and the estimated SEM contour data to sample the SEM contour data on the basis of types of the one-dimensionally and two-dimensionally shaped contours.Type: ApplicationFiled: March 23, 2012Publication date: August 14, 2014Inventors: Takuma Shibahara, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
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Publication number: 20130223723Abstract: The present invention provides a pattern measuring apparatus (600) that: acquires the image contour of a circuit pattern formed by transferring design data; classifies the acquired image contour into shape structures; calculates normal vectors for each shape structure; maps the shape structures to the image contour; uses at least one normal direction for each shape structure to stabilize the normal directions to the image contour; and uses the normal vectors for each shape structure to determine the position of a SEM contour.Type: ApplicationFiled: March 28, 2011Publication date: August 29, 2013Inventors: Takuma Shibahara, Tsuyoshi Minakawa, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo