Patents by Inventor Hitoshi SUGAHARA

Hitoshi SUGAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836906
    Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: December 5, 2023
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shinichi Shinoda, Yasutaka Toyoda, Shigetoshi Sakimura, Masayoshi Ishikawa, Hiroyuki Shindo, Hitoshi Sugahara
  • Patent number: 11443917
    Abstract: The present invention relates to an image generation method for an objective for generating an image corresponding to a multi-frame image from image signals obtained by scanning a small number of frames are proposed.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 13, 2022
    Assignee: Hitachi High-Tech Corporation
    Inventors: Chikako Abe, Hitoshi Sugahara
  • Publication number: 20220036116
    Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Inventors: Shinichi SHINODA, Yasutaka TOYODA, Shigetoshi SAKIMURA, Masayoshi ISHIKAWA, Hiroyuki SHINDO, Hitoshi SUGAHARA
  • Patent number: 11176405
    Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 16, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shinichi Shinoda, Yasutaka Toyoda, Shigetoshi Sakimura, Masayoshi Ishikawa, Hiroyuki Shindo, Hitoshi Sugahara
  • Patent number: 10937628
    Abstract: The purpose of the present invention is to provide a charged particle beam device with which it is possible to identify, to a high degree of accuracy, repeat patterns generated by a multiple exposure method such as SADP or SAQP.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Hitachi High-Tech Corporation
    Inventors: Chikako Abe, Hitoshi Sugahara
  • Publication number: 20210043418
    Abstract: The present invention relates to an image generation method for an objective for generating an image corresponding to a multi-frame image from image signals obtained by scanning a small number of frames are proposed.
    Type: Application
    Filed: June 3, 2020
    Publication date: February 11, 2021
    Inventors: Chikako ABE, Hitoshi SUGAHARA
  • Publication number: 20200134355
    Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.
    Type: Application
    Filed: March 15, 2018
    Publication date: April 30, 2020
    Inventors: Shinichi SHINODA, Yasutaka TOYODA, Shigetoshi SAKIMURA, Masayoshi ISHIKAWA, Hiroyuki SHINDO, Hitoshi SUGAHARA
  • Patent number: 10558127
    Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 11, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Shinichi Shinoda, Yasutaka Toyoda, Hiroyuki Ushiba, Hitoshi Sugahara
  • Publication number: 20190362938
    Abstract: The purpose of the present invention is to provide a charged particle beam device with which it is possible to identify, to a high degree of accuracy, repeat patterns generated by a multiple exposure method such as SADP or SAQP.
    Type: Application
    Filed: January 27, 2017
    Publication date: November 28, 2019
    Inventors: Chikako ABE, Hitoshi SUGAHARA
  • Patent number: 10445875
    Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 15, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
  • Patent number: 10190875
    Abstract: The purpose of the present invention is to provide a pattern measurement condition setting device which appropriately sets a measurement condition for finding out an appropriate exposure condition.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 29, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Shinichi Shinoda, Yasutaka Toyoda, Hiroyuki Ushiba, Hitoshi Sugahara
  • Publication number: 20180247400
    Abstract: A pattern-measuring apparatus and a semiconductor-measuring system are provided which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In particular, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Yasutaka TOYODA, Norio HASEGAWA, Takeshi KATO, Hitoshi SUGAHARA, Yutaka HOJO, Daisuke HIBINO, Hiroyuki SHINDO
  • Patent number: 9990708
    Abstract: An object of the present invention is to provide a pattern-measuring apparatus and a semiconductor-measuring system which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In the present invention for attaining the object described above, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 5, 2018
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Norio Hasegawa, Takeshi Kato, Hitoshi Sugahara, Yutaka Hojo, Daisuke Hibino, Hiroyuki Shindo
  • Publication number: 20170336717
    Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.
    Type: Application
    Filed: December 18, 2015
    Publication date: November 23, 2017
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Shinichi SHINODA, Yasutaka TOYODA, Hiroyuki USHIBA, Hitoshi SUGAHARA
  • Publication number: 20170160082
    Abstract: The purpose of the present invention is to provide a pattern measurement condition setting device which appropriately sets a measurement condition for finding out an appropriate exposure condition.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 8, 2017
    Inventors: Shinichi SHINODA, Yasutaka TOYODA, Hiroyuki USHIBA, Hitoshi SUGAHARA
  • Publication number: 20160005157
    Abstract: An object of the present invention is to provide a pattern-measuring apparatus and a semiconductor-measuring system which are able to obtain an evaluation result for suitably selecting processing with respect to a semiconductor device. In the present invention for attaining the object described above, there is proposed a pattern-measuring apparatus including an arithmetic device which compares a circuit pattern of an electronic device with a reference pattern, in which the arithmetic device classifies the circuit pattern in processing unit of the circuit pattern on the basis of a comparison of a measurement result between the circuit pattern and the reference pattern with at least two threshold values.
    Type: Application
    Filed: February 5, 2014
    Publication date: January 7, 2016
    Inventors: Yasutaka TOYODA, Norio HASEGAWA, Takeshi KATO, Hitoshi SUGAHARA, Yutaka HOJO, Daisuke HIBINO, Hiroyuki SHINDO
  • Patent number: 8959461
    Abstract: A pattern measurement device includes: a storage section storing mask edge data of a circuit pattern and image data obtained by imaging the circuit pattern; an SEM contour extracting section receiving the image data, SEM contour of the circuit pattern, and cause an exposure simulator to generate estimated SEM contour data of an estimated SEM contour on the basis of the mask edge data and SEM contour data of the extracted SEM contour; a shape classifying section receiving the mask edge data, the SEM contour data, and the estimated contour data to classify the SEM contour data and the estimated SEM contour data into a one-dimensionally shaped contour and a two-dimensionally shaped contour; and an SEM contour sampling section receiving the SEM contour data and the estimated SEM contour data to sample the SEM contour data on the basis of types of the one-dimensionally and two-dimensionally shaped contours.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 17, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takuma Shibahara, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
  • Patent number: 8942464
    Abstract: The present invention provides a pattern measuring apparatus (600) that: acquires the image contour of a circuit pattern formed by transferring design data; classifies the acquired image contour into shape structures; calculates normal vectors for each shape structure; maps the shape structures to the image contour; uses at least one normal direction for each shape structure to stabilize the normal directions to the image contour; and uses the normal vectors for each shape structure to determine the position of a SEM contour.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 27, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takuma Shibahara, Tsuyoshi Minakawa, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
  • Publication number: 20140224986
    Abstract: A pattern measurement device includes: a storage section storing mask edge data of a circuit pattern and image data obtained by imaging the circuit pattern; an SEM contour extracting section receiving the image data, SEM contour of the circuit pattern, and cause an exposure simulator to generate estimated SEM contour data of an estimated SEM contour on the basis of the mask edge data and SEM contour data of the extracted SEM contour; a shape classifying section receiving the mask edge data, the SEM contour data, and the estimated contour data to classify the SEM contour data and the estimated SEM contour data into a one-dimensionally shaped contour and a two-dimensionally shaped contour; and an SEM contour sampling section receiving the SEM contour data and the estimated SEM contour data to sample the SEM contour data on the basis of types of the one-dimensionally and two-dimensionally shaped contours.
    Type: Application
    Filed: March 23, 2012
    Publication date: August 14, 2014
    Inventors: Takuma Shibahara, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo
  • Publication number: 20130223723
    Abstract: The present invention provides a pattern measuring apparatus (600) that: acquires the image contour of a circuit pattern formed by transferring design data; classifies the acquired image contour into shape structures; calculates normal vectors for each shape structure; maps the shape structures to the image contour; uses at least one normal direction for each shape structure to stabilize the normal directions to the image contour; and uses the normal vectors for each shape structure to determine the position of a SEM contour.
    Type: Application
    Filed: March 28, 2011
    Publication date: August 29, 2013
    Inventors: Takuma Shibahara, Tsuyoshi Minakawa, Michio Oikawa, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Shindo