Patents by Inventor Hitoshi Wakabayashi
Hitoshi Wakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9153663Abstract: A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.Type: GrantFiled: May 19, 2010Date of Patent: October 6, 2015Assignee: SONY CORPORATIONInventors: Satoru Mayuzumi, Hitoshi Wakabayashi
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Patent number: 8384167Abstract: A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film and having a region protruding from a forming region of the SiGe layer with a second width wider than the first width; and source/drain regions having extension regions formed on the semiconductor substrate which sandwiches the channel forming region, thereby forming a field effect transistor, wherein the extension region is apart from the SiGe layer so that a depletion layer extending from a junction surface between the extension region and the semiconductor substrate does not reach the SiGe layer.Type: GrantFiled: August 17, 2010Date of Patent: February 26, 2013Assignee: Sony CorporationInventors: Yoshiaki Kikuchi, Hitoshi Wakabayashi
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Publication number: 20110042758Abstract: A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film and having a region protruding from a forming region of the SiGe layer with a second width wider than the first width; and source/drain regions having extension regions formed on the semiconductor substrate which sandwiches the channel forming region, thereby forming a field effect transistor, wherein the extension region is apart from the SiGe layer so that a depletion layer extending from a junction surface between the extension region and the semiconductor substrate does not reach the SiGe layer.Type: ApplicationFiled: August 17, 2010Publication date: February 24, 2011Applicant: SONY CORPORATIONInventors: Yoshiaki Kikuchi, Hitoshi Wakabayashi
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Publication number: 20100314694Abstract: A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.Type: ApplicationFiled: May 19, 2010Publication date: December 16, 2010Applicant: SONY CORPORATIONInventors: Satoru Mayuzumi, Hitoshi Wakabayashi
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Patent number: 7830703Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.Type: GrantFiled: May 25, 2005Date of Patent: November 9, 2010Assignee: NEC CorporationInventors: Koichi Takeda, Masahiro Nomura, Kiyoshi Takeuchi, Hitoshi Wakabayashi, Shigeharu Yamagami, Risho Koh, Koichi Terashima, Katsuhiko Tanaka, Masayasu Tanaka
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Patent number: 7723808Abstract: The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region. On a silicon substrate, a device isolation region 102, a gate insulating film 103, a gate electrode 104, an extension 105, and a sidewall insulating film 106 are formed. After that, an elevated region is formed, and a source/drain region 108 and a silicide layer 109 are formed. Subsequently, the sidewall insulating film 106 is etched to provide a gap from the elevated region 107, and a stressed film 110 is buried in the gap.Type: GrantFiled: December 21, 2006Date of Patent: May 25, 2010Assignee: NEC CorporationInventors: Yoshifumi Okuda, Hitoshi Wakabayashi
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Patent number: 7719043Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a pType: GrantFiled: July 4, 2005Date of Patent: May 18, 2010Assignee: NEC CorporationInventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Risho Koh, Kiyoshi Takeuchi, Masahiro Nomura, Koichi Takeda, Koichi Terashima, Masayasu Tanaka, Katsuhiko Tanaka
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Patent number: 7701018Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.Type: GrantFiled: March 22, 2005Date of Patent: April 20, 2010Assignee: NEC CorporationInventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe, Koichi Terashima
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Patent number: 7612416Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.Type: GrantFiled: September 29, 2004Date of Patent: November 3, 2009Assignee: NEC CorporationInventors: Kiyoshi Takeuchi, Koichi Terashima, Hitoshi Wakabayashi, Shigeharu Yamagami, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe
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Publication number: 20090026504Abstract: The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region. On a silicon substrate, a device isolation region 102, a gate insulating film 103, a gate electrode 104, an extension 105, and a sidewall insulating film 106 are formed. After that, an elevated region is formed, and a source/drain region 108 and a silicide layer 109 are formed. Subsequently, the sidewall insulating film 106 is etched to provide a gap from the elevated region 107, and a stressed film 110 is buried in the gap.Type: ApplicationFiled: December 21, 2006Publication date: January 29, 2009Inventors: Yoshifumi Okuda, Hitoshi Wakabayashi
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Publication number: 20090014795Abstract: A ? gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.Type: ApplicationFiled: July 14, 2005Publication date: January 15, 2009Inventors: Risho Koh, Katsuhiko Tanaka, Shigeharu Yamagami, Koichi Terashima, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda
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Publication number: 20080251849Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.Type: ApplicationFiled: March 22, 2005Publication date: October 16, 2008Inventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe, Koichi Terashima
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Publication number: 20080079077Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.Type: ApplicationFiled: May 25, 2005Publication date: April 3, 2008Applicant: NEC CORPORATIONInventors: Koichi Takeda, Masahiro Nomura, Kiyoshi Takeuchi, Hitoshi Wakabayashi, Shigeharu Yamagami, Risho Koh, Koichi Terashima, Katsuhiko Tanaka, Masayasu Tanaka
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Publication number: 20080029821Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a pType: ApplicationFiled: July 4, 2005Publication date: February 7, 2008Applicant: NEC CORPORATIONInventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Risho Koh, Kiyoshi Takeuchi, Masahiro Nomura, Koichi Takeda, Koichi Terashima, Masayasu Tanaka, Katsuhiko Tanaka
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Publication number: 20070257277Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.Type: ApplicationFiled: May 7, 2005Publication date: November 8, 2007Applicant: NEC CORPORATIONInventors: Koichi Takeda, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Shigeharu Yamagami, Masahiro Nomura, Masayasu Tanaka, Koichi Terashima, Risho Koh, Katsuhiko Tanaka
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Publication number: 20070187682Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.Type: ApplicationFiled: August 27, 2004Publication date: August 16, 2007Inventors: Kiyoshi Takeuchi, Koji Watanabe, Koichi Terashima, Atsushi Ogura, Toru Tatsumi, Koichi Takeda, Masahiro Nomura, Masayasu Tanaka, Shigeharu Yamagami, Hitoshi Wakabayashi
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Publication number: 20070132009Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.Type: ApplicationFiled: September 29, 2004Publication date: June 14, 2007Inventors: Kiyoshi Takeuchi, Koichi Terashima, Hitoshi Wakabayashi, Shigeharu Yamagami, Atsushi Ogura, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda, Toru Tatsumi, Koji Watanabe
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Publication number: 20070075372Abstract: There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.Type: ApplicationFiled: October 19, 2004Publication date: April 5, 2007Inventors: Koichi Terashima, Kiyoshi Takeuchi, shigeharu Yamagami, Hitoshi Wakabayashi, Atsushi Ogura, Koji Watanabe, Toru Tatsumi, Koichi Takeda, Masahiro Nomura, Masayasu Tanaka
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Patent number: 6933569Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.Type: GrantFiled: September 24, 2003Date of Patent: August 23, 2005Assignee: NEC CorporationInventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
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Patent number: 6916695Abstract: One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.Type: GrantFiled: July 3, 2002Date of Patent: July 12, 2005Assignee: NEC CorporationInventors: Hitoshi Wakabayashi, Yukishige Saito