Patents by Inventor Hitoshi Wakabayashi

Hitoshi Wakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040129975
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
    Type: Application
    Filed: September 24, 2003
    Publication date: July 8, 2004
    Applicant: NEC CORPORATION
    Inventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
  • Publication number: 20020179975
    Abstract: One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.
    Type: Application
    Filed: July 3, 2002
    Publication date: December 5, 2002
    Inventors: Hitoshi Wakabayashi, Yukishige Saito
  • Patent number: 6483151
    Abstract: One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: November 19, 2002
    Assignee: NEC Corporation
    Inventors: Hitoshi Wakabayashi, Yukishige Saito
  • Publication number: 20010015463
    Abstract: One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.
    Type: Application
    Filed: January 4, 2001
    Publication date: August 23, 2001
    Applicant: NEC CORPORATION
    Inventors: Hitoshi Wakabayashi, Yukishige Saito
  • Patent number: 6121120
    Abstract: In a method for manufacturing a semiconductor device, an impurity diffusion region is formed within a semiconductor substrate. Then, a chemical dry etching process or a heating process is carried out to remove a contamination layer from the impurity diffusion region. Then, a silicon layer is selectively grown on the impurity diffusion region.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventors: Hitoshi Wakabayashi, Toru Tatsumi
  • Patent number: 5593923
    Abstract: A method of producing a semiconductor device having a refractory metal silicide film includes the steps of implanting ions such as silicon into an active region such as drain/source region to form a damage portion therein, depositing a refractory metal on the damage portion, and annealing to form the refractory metal silicide layer. This silicide layer is formed by the refractory metal being reacted with silicon in the damage portion of the active region.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: January 14, 1997
    Assignee: NEC Corporation
    Inventors: Tadahiko Horiuchi, Takashi Ishigami, Hiroyuki Nakamura, Tohru Mogami, Hitoshi Wakabayashi, Takemitsu Kunio, Koichiro Okumura
  • Patent number: 4069394
    Abstract: In a stereophonic sound reproduction system in which stereophonic left and right signals are treated to have a level difference therebetween for establishing a localized sound image spaced from the midpoint between left and right loudspeakers, the level difference between such left and right signals is reduced as the frequency thereof increases for improving the localization of the sound image resulting from the application of the resulting or converted left and right signals to the left and right loudspeakers.
    Type: Grant
    Filed: June 2, 1976
    Date of Patent: January 17, 1978
    Assignee: Sony Corporation
    Inventors: Toshitada Doi, Hitoshi Wakabayashi