Patents by Inventor Ho Dai Truong
Ho Dai Truong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7642832Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: January 22, 2008Date of Patent: January 5, 2010Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20080129360Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: January 22, 2008Publication date: June 5, 2008Applicant: Seiko Epson CorporationInventors: Ho Dai TRUONG, Chong Ming Lin
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Patent number: 7352222Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: April 22, 2005Date of Patent: April 1, 2008Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6900682Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: September 25, 2003Date of Patent: May 31, 2005Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20040056699Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: September 25, 2003Publication date: March 25, 2004Applicant: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6653881Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: October 23, 2002Date of Patent: November 25, 2003Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20030058018Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: October 23, 2002Publication date: March 27, 2003Inventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6489826Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: October 5, 2001Date of Patent: December 3, 2002Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20020017938Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: October 5, 2001Publication date: February 14, 2002Inventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6323711Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: December 1, 2000Date of Patent: November 27, 2001Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20010000018Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: December 1, 2000Publication date: March 15, 2001Inventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6163194Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: August 17, 1999Date of Patent: December 19, 2000Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 5966037Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: February 4, 1997Date of Patent: October 12, 1999Assignee: Seiko Epson Corporation of Tokyo JapanInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 4733108Abstract: An improved on-chip bias generator for producing a negative bias for the substrate of a VLSI FET chip for reducing the body effect and for increasing circuit speed. The improvement comprises active FETs to rectify a ring oscillator square wave output, thereby reducing the voltage losses in the rectifier and increasing the amount of voltage delivered to the substrate.Type: GrantFiled: June 28, 1982Date of Patent: March 22, 1988Assignee: Xerox CorporationInventor: Ho-Dai Truong