Generator with programmable non-overlapping-clock-edge capability

Abstract

A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

1. This application is a continuation of U.S. patent application Ser. No. 09/376,186, filed Aug. 17,1999, which is a continuation of application Ser. No. 08/795,363, filed Feb. 4, 1997, now U.S. Pat. No. 5,966,037, which is a continuation of application Ser. No. 08/478,534, filed Jun. 7, 1995, now abandoned, which is a division of application Ser. No. 08/255,910, filed Jun. 8, 1994, U.S. Pat. No. 5,444,405, which is a continuation of application Ser. No. 07/967,614, filed Oct. 28, 1992, now abandoned, which is a continuation-in-part of application Ser. No. 07/844,066, filed Mar. 2, 1992, now abandoned.

BACKGROUND OF THE INVENTION

2. 1. Field of the Invention

3. The present invention relates generally to a programmable clock generator for integrated circuits, very large scale integrated circuits (VLSI), and ultra large scale integrated circuits (ULSI). More particularly, the present invention relates to a programmable clock generator for selecting optimal non-overlapping clocking signals for controlling elements on a chip.

4. 2. Related Art

5. Most microprocessor chips operate as control driven, synchronous sequential systems. This means the sequence of operations in the system is synchronized by a master clock signal (usually an external clock). This clock signal is usually one of the forms shown in FIG. 1; which illustrates a square wave with a 50% duty cycle.

6. The master clock signal allows system operations to occur at regularly spaced-intervals. In particular, operations on the chip are made to take place at times when the clock signal is making a transition from low-to-high or from high-to-low; rising edge 102 or falling edge 104, respectively.

7. Many microprocessor chips have their timing controlled by two or more related clock signals generated by an on-chip clock generator based on the master clock signal. FIG. 2A illustrates one such combination utilizing two clock signals identified by &phgr;1 and &phgr;2. This clocking arrangement provides four different edges and three different states per period, compared to only two edges and two states per period provided with a single clock signal as shown in FIG. 1. FIG. 2B illustrates examples of the three possible states for clock signals &phgr;1 and &phgr;2. For elements on the chip to function properly, it is important that edges of clock signals &phgr;1 and &phgr;2 are non-overlapping. If the edges overlap there will be more restrictions on data transfer and signal hand shaking.

8. Additionally, it is equally important that non-overlapping clock edges be evenly distributed to all comers of a chip regardless of the distance which those signals must travel. As chip size increases, clock signals &phgr;1 and &phgr;2 have to travel greater distances throughout the chip. This causes clock signals &phgr;1 and &phgr;2 to become degraded. As distances increase, rising edges 202, 206 and failing edges 204, 208 may become obscured (experience phase shifts and increases in transition times) and can overlap. This phenomenon, sometimes referred to as clock skew, is caused by a number of factors, including: loading, unwanted noise, coupling, capacitance, resistance, inductance and other debilitating effects.

9. To account for these factors, designers must separate the rising and falling edges 202, 204, 206, 208 of different clock signals (i.e., &phgr;1 and &phgr;2) with a large enough margin of time to allow for clock skew. For instance, failing edge 204 and rising edge 206 must be separated by a minimum temporal distance or amount of time (7) to avoid overlapping states; especially for level-triggering operations in metal-oxide-silicon (MOS) technology. The larger T is, the less likely the chip will fail due to overlapping signals caused by skewing. The wide range of operating environments to which the chip(s) may be subject must be considered in selecting T. Therefore, to provide an adequate margin, manufacturers are forced to select T large enough to provide functionality in a worst-case environment. However, a large T is a significant cycle time constraint. Therefore chip design is not optimized for each environment.

10. To illustrate this, consider current chip design practices that must account for clock skew by designing a chip with a minimum safety distance T between signals against worst-case conditions. Once T is selected the chip is manufactured and tested. If the chip designer selected a clock speed that has insufficient non-overlapping time, the chip will not function due to overlapping states for some circuits located on the chip. When a chip runs properly, chip designers assume they have chosen the correct frequency, clock states; rise and fall times, and non-overlapping time T. However, chip designers do not know whether a faster clock speed or a smaller T are possible. To find out, chip manufacturers must build entirely new chips with different process parameters, which is inefficient and expensive.

11. Presently, no programming or tweaking can be performed after a chip is finalized. It is possible to have an on-chip clock generator running at different clock frequencies than external crystal oscillators, but the non-overlapping time of the clock edges generated by the clock generator is fixed by circuit hardware. Therefore, what is needed is a flexible system and method of programming an on-chip clock generator at the manufacturing stage to achieve adjustable as well as optimal non-overlapping times T between clock edges.

12. At the post-manufacturing stage, environmental conditions, such as heat and cold can also affect clock skewing. If a chip is manufactured under laboratory conditions, it may function properly. However, temperature changes may cause the chip to malfunction due to skewed clock signals. Therefore, what is needed is an on-chip clock generator that can be dynamically programmed to select non-overlapping times T to account for environmental fluctuations while the chip is in an operational environment, such as a processor chip operating in a computer.

SUMMARY OF THE INVENTION

13. The present invention is directed to a system and method for providing programmable non-overlapping clock generation on a chip. The present invention includes four main embodiments. The first embodiment is directed to the overall operation of an on-chip clock generator. The second embodiment is directed to a hardware programmable clock generation system and method. The third embodiment is directed to a software programmable clock generation system and method. The fourth embodiment is directed to a combination of all three embodiments.

14. The programmable on-chip clock generator provides two phases of a system clock with non-overlapping edges. The programmability of the clock generator provides flexibility during chip fabrication, and when a chip is functioning in a operational environment.

15. During the manufacturing phases of chip production, characteristics of the on-chip clock generator are altered to ensure the edges of the two generated clocks do not overlap. This allows the manufacturer to optimize the performance of the chip while the chip is undergoing initial production testing. This feature obviates the need to perform costly and time consuming trial-and-error design and redesign of on-chip clock generators.

16. Additionally, the present invention provides a technique for optimizing the performance of the on-chip clock generator after the chips have left the manufacturing environment. One feature of the present invention is the ability to adjust clock generation dynamically to account for climatic changes in an operational, or other post-production, environment. This allows chips to be manufactured with wider tolerances and allows operation of the chip to be optimized when the chip is in the operational environment.

17. Adjustments to the on-chip clock generator during the manufacturing phase are referred to as hardware programming because the manufacturer alters the physical composition of the clock generator. Adjustments to the on-chip clock generator once the chip is fabricated and in the operational environment are referred to as software programming. This terminology reflects the fact that through the use of software commands, the characteristics of the on-chip clock generator can be adjusted to compensate for changes in the operating environment. Programming capability in both cases is accomplished by adding or subtracting delay elements in feedback paths within the clock generator circuit.

18. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

19. FIG. 1 illustrates a square wave with a 50% duty cycle.

20. FIG. 2A illustrates two clock signals identified by 01 and 02 with non-overlapping edges.

21. FIG. 2B illustrates three possible states for clock signals 01 and 02.

22. FIG. 3 illustrates a high-level block diagram of an environment in which the present invention operates.

23. FIG. 4 illustrates a high-level block diagram of clock generator according to the present invention.

24. FIG. 5 is a flow chart illustrating the operation of a clock generator according to the present invention.

25. FIG. 6A illustrates a circuit diagram of a clock-to-clock non-overlapping time adjuster according to a hardware embodiment of the present invention.

26. FIG. 6B illustrates a logic circuit diagram of a clock-to-clock non-overlapping time adjuster with generic delay paths.

27. FIG. 6C illustrates a timing diagram of the operation of the clock-to-clock non-overlapping time adjuster.

28. FIG. 7 illustrates an example of hardware programming according to the present invention.

29. FIG. 8A illustrates a circuit diagram of a clock-to-clock non-overlapping time adjuster according to a software embodiment of the present invention utilizing path selection to adjust delay.

30. FIG. 8B illustrates a circuit diagram of a clock-to-clock nonoverlapping time adjuster according to a software embodiment of the present invention utilizing path length selection to adjust delay.

31. In the drawings the left-most digit of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

32. I. General Overview

33. A. Brief Overview

34. The present invention is directed to a system and method for providing non-overlapped clock generation on a chip. The present invention includes four main embodiments. The first embodiment is directed to the overall operation of an on chip clock generator. The second embodiment is directed to a hardware programmable clock generation system and method. The third embodiment is directed to a software programmable clock generation system and method. The fourth embodiment is directed to a combination of the first three embodiments. These embodiments of the present invention are discussed in the following sections.

35. B. Environment

36. FIG. 3 illustrates a high level block diagram of an environment 301 in which the present invention operates. Environment 301 may be a wafer containing hundreds of chips at a fabrication/testing stage or a computer in a user environment. As illustrated, environment 301 includes an external clock generator 302 and a chip 304. In a preferred embodiment, external clock generator 302 is a crystal oscillator, which produces a signal similar to that shown in FIG. 1.

37. Chip 304 has circuit elements 310. Many computers require more than one processor chip. As shown in FIG. 3, an optional co-processor or peripheral chip 305 may be coupled to chip 304.

38. Chip 304 also has an internal clock generator 308, which provides multiple clock signals to elements 310. In a preferred embodiment clock generator 308 provides two clock signals, &phgr;1 and &phgr;2; similar to FIG. 2A. To ensure that active portions of clock signals &phgr;1 and &phgr;2 are non-overlapping, clock generator 308 is programmed to achieve optimal non-overlapping clock generation. Accordingly, clock generator 308 provides a plurality of programmable non-overlapping times between clock signals &phgr;1 and &phgr;2. In the preferred embodiment, clock generator 308 provides the option of selecting between 0.5 ns, 2.5 ns and 4.5 ns of non-overlapping time between clock signals &phgr;1 and &phgr;2 shown as T in FIG. 2A. In alternative embodiments, T must be less than the period of CLKIN 401. Furthermore, for a 50% duty cycle T should be less than the period of CLKIN/2. If this condition is not met, the circuit may chop out clocks.

39. This flexibility permits adjustments to clock generation if there is not enough holding time between clock edges by increasing T between clock signals &phgr;1 and &phgr;2. On the other hand, if there is too much holding time between clock signals &phgr;1 and &phgr;2, T can be decreased. In either case, “tweaking” can be performed while the chip is being tested (during the manufacture stage) without expensive and costly changes to the clock design.

40. Adjustments to clock generator 308 can also be performed in an operational environment (product usage stage). As a result, clock generator 308 can be adjusted for climatic changes which can affect whether clock signals &phgr;1 and &phgr;2 are non-overlapping.

41. II. Clock Generator

42. FIG. 4 illustrates a high level block diagram of clock generator 308. Clock generator 308 includes an input waveform stabilizer 402, a clock-to-clock non-overlapping time adjuster 406, and a clock driver 410 having a two phase output &phgr;1 and &phgr;2 (CLKOUT 411).

43. Operation of clock generator 308 is generally illustrated in the flow chart shown in FIG. 5. In describing the operation of clock generator 308 reference will be made to FIGS. 2-8.

44. Referring now to FIGS. 4 and 5, in a step 502, clock generator 308 receives an external clock signal 401 from external clock 302 shown as “CLKIN” 401 (as shown in FIG. 4). In a step 504, input waveform stabilizer 02 stabilizes CLKIN 401. Waveform stabilizer 402 reshapes CLKIN 401 into a square wave (CLK 405) because CLKIN 401 tends to be distorted due to input jitter, noise from ground bounce and coupling. In the preferred embodiment, waveform stabilizer 402 is a Schmitt trigger. The structure and operation of a Schmitt trigger are well known to those skilled in the art.

45. A. Programming

46. In a step 508, CLK 405 is received by clock-to-clock non-overlapping time adjuster 406, and multiple signals with non-overlapping active phases 407 are generated with adjustable delay between edges. The clock generator 308 can be programmed to provide desired holding times between clock edges.

47. There are two types of programming that can occur: hardware and software. Hardware programming normally occurs during the testing stages of a chip and involves altering the chip physically. This process is typically irreversible. Software programming normally occurs while a chip is functioning in an operational environment. Software programming is dynamic, allowing adjustments to delay time T between clock edges without physically altering the chip. Programming capability in both cases is accomplished by adding or subtracting delay elements in feedback paths within the clock generator circuit (to be described).

48. 1. Hardware Programming

49. FIG. 6A illustrates the hardware embodiment of a clock to clock nonoverlapping time adjuster 406 according to the present invention. Referring to FIG. 6A, clock-to-clock non-overlapping time adjuster 406 includes logic gates 602,603, delay element(s) 604 and drivers 622, 624.

50. In the preferred embodiment, logic gates 602 and 603 are NOR gates and delay elements 604 are inverters. Other logic elements can be substituted for the ones described in the preferred embodiment. For instance, inverter 604 can be replaced with NAND gates having inputs tied together. Additionally, delay elements 604 can be any device (i.e., resistors) that delay a signal.

51. Delay elements 604, form delay paths 606A, 606B (generally 606) which govern the amount of delay between clock signal &phgr;1 and clock signal &phgr;2. Adjusting the length of delay paths 606 by adding or subtracting delay elements 604 coupled to logic gates 602, 603, increases or decreases the amount of time T between edges of clock signals &phgr;1 and &phgr;2. Typically, a chip designer will include more delay elements 604 than needed to afford latitude in the selection of possible delay times. Selection from a plurality of pre-planned delay paths 606 provide a corresponding plurality of non-overlapping optional times between clock edges.

52. FIG. 6B illustrates clock-to-clock non-overlapping time adjuster 406 with generic delay paths or delay segments &phgr;1 and &phgr;2 to delay clock signals &phgr;1 and &phgr;2. Delay segments &tgr;1 and &tgr;2 are equivalent to delay paths 606 shown in FIG. 6A. Changing the amount of delay allows the amount of time between edges of &phgr;1 and &phgr;2 to be adjusted. The amount of delay introduced in these segments &tgr;1 and &tgr;2 is programmable by adding or deleting delay elements 604.

53. Referring to FIG. 6B, time adjuster 406 operates as follows. An input clock signal (CLK) 405 passes through inverter 609 to form inverted clock signal 601 (NOTCLK 601). CLK 405 and NOTCLK 601 are used to form two new clock signals &phgr;1 and &phgr;2. CLK 405 is an input signal to NOR gate 602 along with a delayed signal &phgr;2. NOTCLK 601 is an input signal to NOR gate 603 along with delayed 01 signal.

54. FIG. 6C is a timing diagram illustrating the operation of the clock to clock non-overlapping time adjuster 406 of the present invention. Referring to FIGS. 6B and 6C, the technique of the clock to clock non-overlapping time adjuster 406 will now be described. Note, gate delays, which are shown as t in FIG. 6C, are negligible. Note: t=gate delay; &tgr;-delay of a delay element; and T=t+&tgr;.

55. As shown in FIG. 6C, in the beginning of region 1, clock 405 transitions to a logic high state, which forces 951 to the logic low state. A delay timer &tgr;1 later, delayed &phgr;1 transitions to a low state. Since NOTCLK 601 is at a logic low state, this transition forces &phgr;2 to transition to a logic high state.

56. As a result of delay &tgr;1, the rising transition of &phgr;2 lags behind the falling transition of 451 by the amount of &tgr;1 plus any gate delay times t. The amount of time separating the falling transitions of &phgr;1 from the rising transitions of &phgr;2 is controlled by adjusting &tgr;1. If the circuit designer wishes to increase the clock frequency, 7-1 is programmed to a lesser amount. On the other hand, if the circuit operation is hampered by overlapping falling and rising transitions of &phgr;1 and &phgr;2, respectively, &tgr;1 is increased until this problem is rectified. In this manner, the circuit is optimized by increasing the clock frequency to the maximum permissible level without the transitions overlapping.

57. In a similar fashion, the falling edges of &phgr;2 are separated from the rising edges of &phgr;1 by controlling the amount of delay programmed into &tgr;2. If the delay in &tgr;2 is increased, the separation between the falling edges of &phgr;2 and the rising edges of &tgr;1 is increased, and if the delay in &tgr;2 is decreased, the separation is decreased. Therefore, the circuit can be further optimized by adjusting the time T between the falling edges of &phgr;2 and the rising edges of &phgr;1 .

58. An example of hardware programming is illustrated in FIG. 7. FIG. 7 represents a portion of delay path 606 of FIG. 6A. Programming is accomplished by closing or opening switches 707, 711. When switch 707 is closed, nodes 720 and 722 are shorted together. Additionally, by opening switch 711 delay elements 604A, 604B are completely dropped out of the circuit or “shorted out.” Thus, closing switch 707 and opening switch 711, bypasses delay elements 604A, 604B and decreases the amount of path delay for a signal. Opening switch 707 and closing switch 711 increases the amount of path delay for a signal that passes through delay path 606.

59. There are a number of ways to close or open switches 707, 711. Such techniques include fuse/anti-fuse processing, laser burning, ion beam milling and other techniques. In the preferred embodiment laser “zap” burning technique is used to open/close switches 707, 711.

60. 2. Software Programming

61. FIGS. 8A and 8B are logic level circuit diagrams of a clock-to-clock non-overlapping time adjuster 406 according to a software embodiment of the present invention. FIGS. 8A and 8B are similar to FIG. 6 with the exception of the manner in which the delay elements r are implemented. In other words, the software embodiment operates in a manner similar to that of the hardware embodiment described above. However, in the software embodiment, the delay times &tgr;1 and &tgr;2 are not fixed at the time of fabrication as they are in the hardware embodiment. In the software embodiment, the amount of delay chosen for &tgr;1 and &tgr;2 is selected using software, and can be changed as required to compensate for changes in operating conditions or other operational parameters.

62. FIG. 8A illustrates a software embodiment using path selection to adjust delay times &tgr;1 and &tgr;2. Referring to FIG. 8A, multiple paths (generally 822) are established on the chip, each having different propagation delay times. The paths 822 are duplicated for &tgr;1 and &tgr;2. Delay paths 822 can be implemented using a multiplicity of delay elements. FIG. 8A shows delay paths 822 made up of inverters 604. If inverters are chosen, an even number must be used in each path 822 for proper operation.

63. The manner of path selection will now be described. Control words 850A, 850B are generated and sent to demultiplexers 824A, 824B selecting the paths to be followed. Control words 850A, 850B are also sent to multiplexers 825A, 825B for selecting paths to be followed. Control words 850A, 850B command demultiplexers 824A, 824B and multiplexers 825A, 825B to route the signals output from NOR-gates 826A, 826B, respectively, through a specified path 822. The amount of delay, therefore, varies depending on the propagation delay of the selected path 822.

64. FIG. 8B illustrates a software embodiment using path-length selection to adjust delay times &tgr;1 and &tgr;2. In this embodiment paths 842A, 842B are made up of strings of delay elements 846 and multiple connection points 848. Control words 850 are sent to switches 844A, 844B. The control words 850A, 850B ‘command’ switch 844A, 844B, respectively to select the signal at one of connection points 848 along the string. The farther along the string connection point 848 is chosen, the longer the delay time will be. Switches 844A, 844B are multiplexers.

65. Strings 842A, 842B are shown in FIG. 8B as being implemented using inverters as the delay elements 846. If inverters are used, the paths must be chosen such that only an even number of inverters can be selected to make up the delay of the signal. A number of other elements 846 can also be chosen to make up delay paths 842A, 842B.

66. B. Combination Embodiment

67. The present invention can be implemented using a combination of the hardware and software embodiments described above. For example, the delay strings can be first adjusted to a maximum delay time as described in the hardware embodiment. Then, fine tuning can be accomplished in the operational environment using the software embodiments described above.

68. While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A programmable clock generator for providing multiple clock signals with non-overlapping edges, comprising:

means for receiving an external signal from an external clock and providing first and second clock signals as a result of said external signal;

first programmable delay means, coupled to said receiving means, for delaying said first clock signal and feeding a resultant delayed first clock signal back into said receiving means to change the phase of said second clock signal based on the amount of delay introduced by said first programmable delay means; and

second programmable delay means coupled to said receiving means, for delaying said second clock signal and feeding a resultant delayed second clock signal back into said receiving means to change the phase of said first clock signal based on the amount of delay introduced by said second programmable delay means.

2. The programmable clock generator of

claim 1, wherein said means for receiving comprises:

a first logic gate, having first and second input terminals and a first output terminal, said first input terminal coupled to the said external clock for receiving said external clock signal, wherein said first output terminal produces said first clock signal;

a second logic gate, having third and fourth input terminals and a second output terminal, said fourth input terminal having an inverter coupled to said external clock for inverting said external clock signal, wherein said output terminal of said second logic gate produces said second clock signal.

3. The programmable clock generator of

claim 1, wherein said first and second programmable delay means each comprise:

a plurality of delay elements connected in series to form a delay path; and

means for altering the number of delay elements comprising said delay.

4. The programmable clock generator according to

claim 3, wherein said means for altering comprises:

a conductive path having a switch, said conductive path connected in parallel with a delay element in said delay path, operable to short out said delay when said switch is closed.

5. The programmable clock generator according to

claim 3, wherein said means for altering comprises:

a plurality of connection points at different locations along said delay path; and

a programmable switch for receiving a delayed clock signal from each of said connection points and selecting one of said delayed clock signals.

6. The programmable clock generator according to

claim 1, wherein said first and second programmable delay means each comprise:

a plurality of delay paths each having a different delay time; and

means for selecting one of said delay paths.

7. A programmable clock generator for receiving a single clock signal and for providing multiple clock signals having non-overlapping clock edges with adjustable distances between said non-overlapping clock edges, comprising:

a first logic gate, having a first and second input terminals and a first output terminal, said first input terminal coupled to the single clock signal for receiving the single clock signal, wherein said first output terminal produces a first clock signal having edges;

a second logic gate, having third and fourth input terminals and a second output terminal, said fourth input terminal having an inverter coupled to the single clock signal for inverting the single clock signal, wherein said output terminal of said second logic gate produces a second clock signal having edges;

a first programmable delay path, coupled between said first output terminal and said third input terminal, for controlling distances between said clock edges of said first and second clock signals; and

a second programmable delay path, coupled between said second output terminal of said second logic gate and said second input terminal of said first logic gate, for controlling distances between said clock edges of said first and second clock signals.

8. The programmable clock generator of

claim 7, wherein said first programmable delay path comprises:

a first conductive path comprising delay elements for delaying said first clock signal, said first conductive path having an input node and an output node; and

a second conductive path coupled to said input and output nodes in parallel to said delay elements, said second conductive path having a first switch whereby said first clock signal bypasses said first conductive path via said second conductive path when said first switch is closed and said input node and said output node are shorted together.

9. The programmable clock generator of

claim 8, wherein said first conductive path further comprises a second switch coupled to said output node and said delay elements operable to be opened when said first switch is closed.

10. The programmable clock generator of

claim 7, wherein said second programmable delay path comprises:

a first conductive path comprising delay elements for delaying said second clock signal, said first conductive path having an input node and an output node; and

a second conductive path coupled to said input and output nodes in parallel to said delay elements, said second conductive path having a first switch whereby said second clock signal bypasses said first conductive path via said second conductive path, when said first switch is closed and said input node and said output node are shortened together.

11. The programmable clock generator of

claim 10, wherein said second conductive path further comprises a second switch coupled to said output node and said delay elements operable to be opened when said first switch is closed.

12. A method of generating non-overlapping clocks, comprising the steps of:

(a) receiving an external clock signal and inverting said external clock signal to provide an inverted clock signal;

(b) generating a first clock signal and a second clock signal based on said external clock signal and aid inverted external clock signal, respectively;

(c) delaying said first clock signal by an adjustable amount of delay to provide a delayed first clock signal and using said delayed first clock signal to alter the phase of said second clock signal;

(d) delaying said second clock signal by an adjustable amount of delay to provide a delayed second clock signal and using said delayed second clock signal to alter the phase of said first clock signal; and

(e) adjusting said amount of delay introduced in steps (c) and (d) to optimize edge placement of said first and second clock signals.

13. The method of

claim 12, wherein said step (c) comprises the step of routing said first clock signal through a first delay path comprising a plurality of discrete delay elements.

14. The method of

claim 12, wherein said step (d) comprises the step of routing said second clock signal through a second delay path comprising a plurality of discrete delay elements.

15. The method of

claim 12, wherein said step (e) comprises the step of shunting at a delay element to bypass said delay element and thereby alter the number of delay elements in at least one of said first and second delay paths.

16. The method of

claim 12, wherein said step (c) comprises the step of routing said first clock signal through a first delay path comprising a plurality of discrete delay elements and first connection points.

17. The method of

claim 12, wherein said step (d) comprises the step of routing said second clock signal through a second delay path comprising a plurality of discrete delay elements and second connection points.

18. The method of

claim 12, wherein said step (e) comprises the step of selecting said first and second delayed clock signal from among said plurality of first and second connection points, respectively.

19. The method of

claim 12, wherein said step (e) comprises the steps of:

selecting a first delay path from a first plurality of delay paths of varying length;

routing said first clock signal through said first delay path to provide said delayed first clock signal;

selecting a second delay path from a second plurality of delay paths of varying length; and

routing said second clock signal through said second delay path to provide said delayed second clock signal.