Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing processes for improving reverse recovery time by converting a power MOSFET which is a majority carrier device to diode having two terminals. Such a MOS control diode can be achieved by forming a discontinuous area in a gate oxide film formed on the surface of a semiconductor substrate so that the conductive gate electrode is connected to the semiconductor substrate. Also, it is possible to form a trench in the semiconductor substrate, to form the gate oxide films on the sidewall of a trench, and to connect the gate electrode to the semiconductor substrate through the bottom of the trench.

Abstract: A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing processes for improving reverse recovery time by converting a power MOSFET which is a majority carrier device to diode having two terminals. Such a MOS control diode can be achieved by forming a discontinuous area in a gate oxide film formed on the surface of a semiconductor substrate so that the conductive gate electrode is connected to the semiconductor substrate. Also, it is possible to form a trench in the semiconductor substrate, to form the gate oxide films on the sidewall of a trench, and to connect the gate electrode to the semiconductor substrate through the bottom of the trench.

Abstract: A test mode setup circuit for a microcontroller unit (MCU) operates a test mode for an internal circuit or the like using only a reset pin and a clock pin, which are required pins. Thus, the microcontroller uses the test mode setup circuit without providing a separate test pin. The test mode setup circuit is suitable for an MCU having a small number of pins. In addition, various test modes for the microcontroller can be achieved by decoding a test mode count value of a test mode counter in alternative ways.

Abstract: A semiconductor diode device having the characteristic of soft recovery and a method for manufacturing the same. A first N+ layer contacts with a cathode electrode. An N- epitaxial layer is formed on the first N+ layer. A P- layer is formed to have an undulating junction with the N- epitaxial layer. A second N+ layer is embedded in the P- layer. An anode electrode is attached to the P- layer, wherein the anode contact to the P- layer includes the second N+ layer. A channel stop region and insulating layer are also added to the structure.

Abstract: 052450152 A power noise preventing circuit for a microcontroller unit (MCU) is provided that prevents an erroneous operation of the MCU caused by power supply noise. The power noise preventing circuit for the MCU can include a power fail detecting circuit that controls a power fail signal by comparing supplied power to a preset fail voltage of a MCU and a system clock generating circuit that receives a clock signal and generates a first system clock signal that determines a state of a system. A clock freezing and synchronizing circuit fixedly outputs a second system clock signal at a state of the first system clock signal when the power falls below the preset fail voltage and the power fail signal is enabled. The clock freezing and synchronizing circuit further outputs the second system clock signal synchronized with the first system clock signal when the power fail signal is disabled.

Abstract: In an on-screen display (OSD) circuit and position detector, the OSD circuit includes a menu OSD circuit for outputting video signals Rm, Gm and Bm and switch signal Ym, a pointer OSD circuit for selecting displayed menu items and for outputting video signals Rp, Gp and Bp and switch signal Yp, and a pointer or menu selecting circuit for receiving the video signals of the menu OSD circuit, Rm, Gm and Bm and switch signal Ym as inputs, and receiving the video signals of the pointer OSD circuit, Rp, Gp and Bp and switch signal Yp as inputs to then first select the output of the pointer OSD circuit, and then to selectively output the output of the menu OSD circuit if there is no output from the pointer OSD circuit.

Abstract: An IGBT (Insulated Gate Bipolar Transistor) is composed of a P.sup.+ silicon substrate, a first epitaxial layer in which the first conductive type high density impurities are composed at a gentle slope, a semiconductor substrate which is located at the above first epitaxial layer and composed of a second epitaxial layer formed of the first conductive type low density impurities, a P.sup.- well which is composed at the surface part of the second epitaxial layer, an active area which is formed and included in the P.sup.- well, and a gate electrode which is folded with part of the edge of the P.sup.- well, included by an insulated oxidation film and formed on the semiconductor substrate. The first epitaxial layer corresponding to the lower part of the above P.sup.

Abstract: An improved font ROM control circuit for an on-screen display capable of performing a function of an on-screen display RAM using an address ROM by storing a coded character address and a coded character color data in a plurality of address ROMs and to selectively output data, thereby to cope with an increasing needs of an on-screen display RAM having a large space, which includes an address signal generation circuit for outputting a readout address signal; an on-screen display RAM for storing a character address and a character color data of a character data in according to a record address signal outputted from a central processing unit and for outputting a previously stored character address and a character color data in accordance with a readout address signal; an address ROM for outputting character addresses and character color data in accordance with a readout address signal outputted from the address generation circuit; a memory selection register for outputting a memory selection signal so as to selec

Abstract: An on-screen display circuit comprising a moving clock generator for generating a moving clock signal and a character moving clock signal in response to a vertical synchronous signal, the moving clock signal varying a horizontal display position value, the character moving clock signal indicating that information to be displayed on a screen has been moved by a horizontal width of one character, a horizontal position detector for generating a horizontal position signal in response to the moving clock signal and the character moving clock signal from the moving clock generator, a vertical position signal and vertical and horizontal clock signals and outputting the generated horizontal position signal to a horizontal dot clock generator, the horizontal position signal designating a horizontal position of a character to be displayed on the screen, a display off signal generator for generating a display off signal in response to the vertical and horizontal clock signals, and a RAM address generator for generating