Abstract: The present disclosure relates to a joint system of a power cable, in which pressure-resistance performance of a boundary area between a power cable and a joint box for connecting power cables is improved.

Abstract: The present disclosure relates to a power cable and an intermediate connection structure, for connection thereof, which is capable of preventing the concentration of stress on a soldered part, which is configured to join a metal sheath of the power cable and a metal sheath restoration layer of the intermediate connection structure while ensuring airtight or watertight sealing therebetween, preventing deformation of or damage to the soldered part due to stress applied thereto, and minimizing thermal history in the power cable during the formation of the soldered part.

Abstract: The present disclosure relates to a power cable and an intermediate connection structure, for connection thereof, which is capable of preventing the concentration of stress on a soldered part, which is configured to join a metal sheath of the power cable and a metal sheath restoration layer of the intermediate connection structure while ensuring airtight or watertight sealing therebetween, preventing deformation of or damage to the soldered part due to stress applied thereto, and minimizing thermal history in the power cable during the formation of the soldered part.

Abstract: The present disclosure relates to a power cable joint system capable of minimizing expansion, deformation or damage of a metal sheath restoration layer, which is formed of a material such as lead sheath, due to internal expansion due to heat generated in an intermediate connection part of the power cable joint system.

Abstract: The present disclosure relates to an intermediate connection structure of a power cable, which is capable of reducing heating of a connecting part of conductors of a pair of power cables connected through a joint box, enhancing a connected state of the conductors, and minimizing a diameter of the conductor connection part.

Abstract: A memory interface may include: a transceiver module configured to exchange signals with a plurality of dies; and an input/output (I/O) rate controller configured to calculate per-signal-interval ratios of each of the dies by monitoring signals transmitted to, and received from, each of the dies, select a first die whose operating time is relatively slow and a second die whose operating time is relatively fast, among the plurality of dies, using the calculated per-signal-interval ratios, and provide the transceiver module with information for adjusting data interval ratios for each of the first and second dies.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.

Abstract: A memory controller for controlling an operation of a device may include a command queue, a command queue controller, and a command information storage. The command queue may store a plurality of commands. The command queue controller may control an operation of the command queue using a pop signal and a push signal. The command information storage may store command information corresponding to each of the commands stored in the command queue. The command queue controller may control the command queue by checking the commands stored in the command queue based on the command information and converting the checked commands based on a result of the checking.

Abstract: The present disclosure relates to a power cable joint system capable of minimizing expansion, deformation or damage of a metal sheath restoration layer, which is formed of a material such as lead sheath, due to internal expansion due to heat generated in an intermediate connection part of the power cable joint system.

Abstract: The present invention disclosure relates to an intermediate connection structure of a power cable, which is capable of reducing heating of a connecting part of conductors of a pair of power cables connected through a joint box, enhancing a connected state of the conductors, and minimizing a diameter of the conductor connection part.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.

Abstract: A memory interface may include: a transceiver module configured to exchange signals with a plurality of dies; and an input/output (I/O) rate controller configured to calculate per-signal-interval ratios of each of the dies by monitoring signals transmitted to, and received from, each of the dies, select a first die whose operating time is relatively slow and a second die whose operating time is relatively fast, among the plurality of dies, using the calculated per-signal-interval ratios, and provide the transceiver module with information for adjusting data interval ratios for each of the first and second dies.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.

Abstract: A memory controller controls an operation of a semiconductor memory device including a plurality of memory cells at a request of a host. The memory controller includes a data conversion unit. The data conversion unit converts first data from the host by comparing the first data with second data programmed previously.

Abstract: Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.

Abstract: Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.

Abstract: Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.

Abstract: Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.

Abstract: A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing RS (Read Status) commands to memory dies included in a first memory die group among the memory dies, issuing the RS commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the RS commands, and resetting an issue period of the RS commands in response to a change of the memory dies to which the RS commands are issued.

Abstract: A memory controller for controlling an operation of a device may include a command queue, a command queue controller, and a command information storage. The command queue may store a plurality of commands. The command queue controller may control an operation of the command queue using a pop signal and a push signal. The command information storage may store command information corresponding to each of the commands stored in the command queue. The command queue controller may control the command queue by checking the commands stored in the command queue based on the command information and converting the checked commands based on a result of the checking.