Abstract: A memory controller for controlling an operation of a device may include a command queue, a command queue controller, and a command information storage. The command queue may store a plurality of commands. The command queue controller may control an operation of the command queue using a pop signal and a push signal. The command information storage may store command information corresponding to each of the commands stored in the command queue. The command queue controller may control the command queue by checking the commands stored in the command queue based on the command information and converting the checked commands based on a result of the checking.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer manager. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.

Abstract: A memory controller controls an operation of a semiconductor memory device including a plurality of memory cells at a request of a host. The memory controller includes a data conversion unit. The data conversion unit converts first data from the host by comparing the first data with second data programmed previously.

Abstract: A data storage device includes a memory device suitable for storing and outputting data in synchronization with a strobe signal; and a controller suitable for delaying the strobe signal based on each of different test delay values, testing capture of the data by using a delayed strobe signal, and determining a delay value of the strobe signal based on a test result.

Abstract: A data storage device includes a memory device suitable for storing and outputting data in synchronization with a strobe signal; and a controller suitable for delaying the strobe signal based on each of different test delay values, testing capture of the data by using a delayed strobe signal, and determining a delay value of the strobe signal based on a test result.

Abstract: A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing RS (Read Status) commands to memory dies included in a first memory die group among the memory dies, issuing the RS commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the RS commands, and resetting an issue period of the RS commands in response to a change of the memory dies to which the RS commands are issued.

Abstract: A semiconductor system includes a semiconductor device suitable for receiving and performing a plurality of commands and a controller suitable for determining whether the semiconductor device completes an operation for each of the plurality of commands by performing one or more status reads for the semiconductor device whenever each of the plurality of commands is issued to the semiconductor device. The controller issues a first command among the plurality of commands to the semiconductor device, performs the one or more status reads for the semiconductor device to store a time taken to perform the first command as operation time information. The controller issues a second command among the plurality of commands to the semiconductor device, waits for a first wait time determined by the operation time information, and then performs the one or more status reads for the semiconductor device.

Abstract: A semiconductor system includes a semiconductor device suitable for receiving and performing a plurality of commands and a controller suitable for determining whether the semiconductor device completes an operation for each of the plurality of commands by performing one or more status reads for the semiconductor device whenever each of the plurality of commands is issued to the semiconductor device. The controller issues a first command among the plurality of commands to the semiconductor device, performs the one or more status reads for the semiconductor device to store a time taken to perform the first command as operation time information. The controller issues a second command among the plurality of commands to the semiconductor device, waits for a first wait time determined by the operation time information, and then performs the one or more status reads for the semiconductor device.

Abstract: A data storage device includes: a first memory device. a second memory device configured to share a write control signal and a read control signal which are provided to the first memory device. and a controller configured to control the first and second memory devices, wherein the controller provides the write control signal and the read control signal to the first and second memory devices at the same time, the first memory device receives only the read control signal according to a first mask signal, and the second memory device receives only the write control signal according to a second mask signal.