Abstract: In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Abstract: One embodiment of the present invention provides a welding wire accommodation-container cover comprising: a blocking part which has a shape corresponding to a transverse cross section of a container body part, and which covers the opening of the container body part; side-forming parts which are connected to the blocking part, and which are bent from the blocking part so as to be fitted to encompass the outer side surface of the upper portion of the container body part; side-fixing parts which are alternately provided with the side-forming parts along the side of the blocking part, and which fix neighboring side-forming parts; and a cut part which is formed at the blocking part, and which can be cut so that a welding wire wound around the container body part can be withdrawn to the outside.

Abstract: An embodiment of the present invention provides a storage container for welding wire, the storage container comprising: an outer shell which has an outer bottom support portion formed at the bottom thereof and within which a wire storage portion for storing coiled welding wire is formed; a bottom part which is seated on and coupled to the outer bottom support portion; an inner shell which comes into close contact with the inner surface of the outer shell and has an inner bottom support portion formed at the bottom thereof and seated on the bottom part; and a cover which is formed to correspond to the shape of the outer shell and closes the top of the outer shell.

Abstract: An embodiment of the present invention provides a retainer ring for welding wire, the retainer ring comprising: a pressure plate which is disposed on a welding wire stack wound and stored in a receiving container so as to press the welding wire stack, and has an opening formed at the center thereof; and a plurality of guide wings which are provided at the outer circumference of the pressure plate to come into contact with the inner wall of the receiving container and each comprise a flexible body that can be changed in shape.

Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.

Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.

Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.

Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.

Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.