Patents by Inventor Ho-Kyu Kang

Ho-Kyu Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10718977
    Abstract: A liquid crystal display according to an exemplary embodiment of the present system and method includes a first insulation substrate, a thin film transistor disposed on the first insulation substrate, a pixel electrode connected to the thin film transistor, a protrusion disposed on the pixel electrode, a second insulation substrate facing the first insulation substrate, a common electrode disposed on the second insulation substrate, and a liquid crystal layer disposed between the pixel electrode and the common electrode, wherein one pixel includes a thin film transistor formation region where the thin film transistor is disposed and a display area where the pixel electrode is disposed, and the protrusion is disposed to overlay at least a portion of edges of the display area.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: July 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youn Hak Jeong, Wan Namgung, Hong Min Yoon, Ho Jun Lee, Pil Gyu Kang, Seung Kyu Lee, Yun Seok Lee
  • Patent number: 10530469
    Abstract: A method for communicating with a network by a terminal in a wireless communication system, wherein the terminal receives, from the network, signaling information representing a transmission period and a time offset for uplink transmission of a feedback information, and determines a time to transmit the feedback information based on the transmission period and the time offset. The terminal transmits the feedback information to the network based on the determined time.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Yu-Suk Yun, Soon-Young Yoon, Hee-Won Kang, Jae-Heung Yeom, Sang-Hyun Yang, Hoon Huh, Youn-Sun Kim, Ho-Kyu Choi, Jae-Sung Jang
  • Publication number: 20190240578
    Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: Jung Kyu YE, Geon Yeong KIM, Chang Hoon YI, Joo Seok LEE, Guhyun PARK, Young Suk KIM, Jae Hyun PARK, June Sik YI, Hun Joon HA, Nak Hyun KIM, Ho Sik KIM, Jeong Min SEO, Tae Hoon KOO, Duc Chun KIM, Seoung Hwi JUNG, Byung Eun JIN, Jin Woo LEE, Seok Hyun KIM, Ju Yong LIM, Hyun Ju CHO, Sang Yeop LEE, Min Kwan CHAE, Sang Ho KIM, Hee Seok KANG, Seongkwan LEE, Jeong Pyo HONG, Choong Yeol LEE, Yong Woo PARK, Kyoung Su LEE, Yu Ju KIM, Dong Gook LEE, Hyun Jin KIM, Hyun Jeong LEE, Dong Young CHANG, Jong Min LEE, Jin Woo LEE, Song I HAN, Taek Ki LEE, Eun Ji NAM, Choon Hwa LEE, Young Min KANG, Jung Soo LEE
  • Patent number: 10315112
    Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 11, 2019
    Assignee: Nexon Korea Corporation
    Inventors: Jung Kyu Ye, Geon Yeong Kim, Chang Hoon Yi, Joo Seok Lee, Guhyun Park, Young Suk Kim, Jae Hyun Park, June Sik Yi, Hun Joon Ha, Nak Hyun Kim, Ho Sik Kim, Jeong Min Seo, Tae Hoon Koo, Duc Chun Kim, Seoung Hwi Jung, Byung Eun Jin, Jin Woo Lee, Seok Hyun Kim, Ju Yong Lim, Hyun Ju Cho, Sang Yeop Lee, Min Kwan Chae, Sang Ho Kim, Hee Seok Kang, Seongkwan Lee, Jeong Pyo Hong, Choong Yeol Lee, Yong Woo Park, Kyoung Su Lee, Yu Ju Kim, Dong Gook Lee, Hyun Jin Kim, Hyun Jeong Lee, Dong Young Chang, Jong Min Lee, Jin Woo Lee, Song I Han, Taek Ki Lee, Eun Ji Nam, Choon Hwa Lee, Young Min Kang, Jung Soo Lee
  • Publication number: 20150041944
    Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.
    Type: Application
    Filed: September 8, 2014
    Publication date: February 12, 2015
    Inventors: Hong-ki KIM, Ho-Kyu KANG, June-taeg LEE, Jae-Hee CHOI
  • Patent number: 8847297
    Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, June-Taeg Lee, Jae-Hee Choi
  • Publication number: 20110163364
    Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.
    Type: Application
    Filed: December 23, 2010
    Publication date: July 7, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, June-Taeg Lee, Jae-Hee Choi
  • Patent number: 7586159
    Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Ho Lee, Ho-Kyu Kang, Yun-Seok Kim, Seok-Joo Doh, Hyung-Suk Jung
  • Patent number: 7294546
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Publication number: 20070176242
    Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
    Type: Application
    Filed: March 21, 2007
    Publication date: August 2, 2007
    Inventors: Jong-Ho Lee, Ho-Kyu Kang, Yun-Seok Kim, Seok-Joo Doh, Hyung-Suk Jung
  • Publication number: 20070004133
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Application
    Filed: September 12, 2006
    Publication date: January 4, 2007
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Patent number: 7112849
    Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: September 26, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Dong-Ho Ahn, Ho-Kyu Kang, Geum-Jong Bae
  • Patent number: 7052967
    Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-jeong Lee, Ho-kyu Kang
  • Patent number: 6930343
    Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-bong Choi, Jo-won Lee, Ho-kyu Kang, Chung-woo Kim
  • Publication number: 20050142706
    Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.
    Type: Application
    Filed: February 17, 2005
    Publication date: June 30, 2005
    Inventors: Dong-Ho Ahn, Ho-Kyu Kang, Geum-Jong Bae
  • Publication number: 20050098839
    Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
    Type: Application
    Filed: September 1, 2004
    Publication date: May 12, 2005
    Inventors: Jong-Ho Lee, Ho-Kyu Kang, Yun-Seok Kim, Seok-Joo Doh, Hyung-Suk Jung
  • Patent number: 6881645
    Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ho Ahn, Ho-Kyu Kang, Geum-Jong Bae
  • Publication number: 20040095837
    Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 20, 2004
    Inventors: Won-Bong Choi, Jo-Won Lee, Ho-Kyu Kang, Chung-Woo Kim
  • Publication number: 20040084709
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 6, 2004
    Applicant: Samsung Electronics Co, Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Publication number: 20030168717
    Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 11, 2003
    Inventors: Hae-Jeong Lee, Ho-Kyu Kang