Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.

Abstract: Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: Disclosed is a method for forming interconnection lines using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer. A HSQ layer is formed over a semiconductor substrate and an entire surface of the HSQ layer is subjected to plasma treatment. It is then possible to pattern the HSQ layer using photo etching, for the bond structure density of an upper part of the HSQ layer has been increased due to the plasma treatment. An opening is formed by patterning the treated HSQ layer and then a conductive layer filling the opening is formed. In this manner, a multilayer interconnection structure can be formed with a low dielectric layer made of HSQ, thereby reducing the resistance-capacitance (RC) delay.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A method of fabricating a gate of a semiconductor device, by which damage to a gate oxide layer is repaired, is provided. In an aspect of the method, a gate oxide layer is formed on a semiconductor substrate. A conductive layer containing silicon is formed on the gate oxide layer. A stacked structure with a polycrystalline silicon layer and a dichlorosilane-family tungsten silicide layer can be used as the conductive layer. A gate is formed by patterning the conductive layer. A silicon source layer which covers the sidewall of the gate is formed by selective epitaxial growth of silicon. The silicon source layer is grown to a thickness of about 200 Å or less. The silicon source layer is thermally treated at an oxidation atmosphere, thus repairing damage to the gate oxide layer.

Abstract: Trench isolation methods for integrated circuit substrates may be simplified by eliminating the steps of forming a silicon nitride layer, etching the silicon nitride layer and removing the silicon nitride layer. In particular, a silicon nitride-free mask pattern, such as a photoresist mask pattern, may be formed on a silicon nitride-free integrated circuit substrate. The silicon nitride-free integrated circuit substrate is etched through the silicon nitride-free mask pattern to form a trench in the substrate. An insulating layer is formed in the trench and is chemical-mechanical polished to form a trench isolating layer. By eliminating the silicon nitride layer, simplified processing and improved performance may be obtained.

Abstract: A capacitor structure of a DRAM device and a method thereof, including a first electrode formed in each unit memory cell to be connected to a source of a transistor, a deteriorating prevention film formed at the lowermost surface of the first electrode, exclusive of a portion where the first electrode is connected to the source of a transistor, an underlayer formed beneath the deterioration prevention film, an undercut formed between the underlayer and deterioration prevention film, a high-dielectric film formed on surfaces of the first electrode, underlayer and deterioration prevention film which is exposed by the undercut, a reaction/diffusion prevention film formed on the high-dielectric film, formed on the first electrode and underlayer, exclusive of an area around the undercut, and a second electrode formed on the entire surface of the high-dielectric film and reaction/diffusion prevention film, thereby preventing increase of leakage current amount caused by the undercut formed during the capacitor manuf