Patents by Inventor Ho-rang Jang

Ho-rang Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210181785
    Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 17, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Rang JANG, Ji-Woong KWON, Sang-Wook HAN
  • Patent number: 10936009
    Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Rang Jang, Ji-Woong Kwon, Sang-Wook Han
  • Patent number: 10862526
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: December 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Huh, Ho-Rang Jang, Seok-Chan Kim, In-Tae Kang, Sang-Heon Lee, Kwan-Yeob Chae, June-Hee Lee, Sang-Hune Park, Jae-Chol Lee, Hyung-Kweon Lee
  • Publication number: 20200036409
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: JUN-HO HUH, HO-RANG JANG, SEOK-CHAN KIM, IN-TAE KANG, SANG-HEON LEE, KWAN-YEOB CHAE, JUNE-HEE LEE, SANG-HUNE PARK, JAE-CHOL LEE, HYUNG-KWEON LEE
  • Patent number: 10516433
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Huh, Ho-Rang Jang, Seok-Chan Kim, In-Tae Kang, Sang-Heon Lee, Kwan-Yeob Chae, June-Hee Lee, Sang-Hune Park, Jae-Chol Lee, Hyung-Kweon Lee
  • Patent number: 10476547
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Huh, Ho-Rang Jang, Seok-Chan Kim, In-Tae Kang, Sang-Heon Lee, Kwan-Yeob Chae, June-Hee Lee, Sang-Hune Park, Jae-Chol Lee, Hyung-Kweon Lee
  • Publication number: 20190196532
    Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.
    Type: Application
    Filed: October 19, 2018
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Rang JANG, Ji-Woong KWON, Sang-Wook HAN
  • Publication number: 20180323820
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Inventors: JUN-HO HUH, HO-RANG JANG, SEOK-CHAN KIM, IN-TAE KANG, SANG-HEON LEE, KWAN-YEOB CHAE, JUNE-HEE LEE, SANG-HUNE PARK, JAE-CHOL LEE, HYUNG-KWEON LEE
  • Patent number: 10050661
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Huh, Ho-Rang Jang, Seok-Chan Kim, In-Tae Kang, Sang-Heon Lee, Kwan-Yeob Chae, June-Hee Lee, Sang-Hune Park, Jae-Chol Lee, Hyung-Kweon Lee
  • Publication number: 20180062692
    Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: JUN-HO HUH, HO-RANG JANG, SEOK-CHAN KIM, IN-TAE KANG, SANG-HEON LEE, KWAN-YEOB CHAE, JUNE-HEE LEE, SANG-HUNE PARK, JAE-CHOL LEE, HYUNG-KWEON LEE
  • Patent number: 9882711
    Abstract: A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: January 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Rang Jang, Suh Ho Lee, Tomas Scherrer, Jun Ho Huh, Chul Jin Kim
  • Publication number: 20180013546
    Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
    Type: Application
    Filed: August 15, 2017
    Publication date: January 11, 2018
    Inventors: Ho Rang Jang, Suh Ho Lee, Tomas Scherrer, Jun Ho Huh, Chul Jin Kim
  • Patent number: 9755821
    Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Rang Jang, Suh Ho Lee, Tomas Scherrer, Jun Ho Huh, Chul Jin Kim
  • Publication number: 20160294544
    Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
    Type: Application
    Filed: March 17, 2016
    Publication date: October 6, 2016
    Inventors: Ho Rang Jang, Suh Ho Lee, Tomas Scherrer, Jun Ho Huh, Chul Jin Kim
  • Patent number: 7356466
    Abstract: A method and apparatus for calculating an observation probability includes a first operation unit that subtracts a mean of a first plurality of parameters of an input voice signal from a second parameter of an input voice signal, and multiplies the subtraction result to obtain a first output. The first output is squared and accumulated N times in a second operation unit to obtain a second output. A third operation unit subtracts a given weighted value from the second output to obtain a third output, and a comparator stores the third output for a comparator stores the third output in order to extract L outputs therefrom, and stores the L extracted outputs based on an order of magnitude of the extracted L outputs.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Ho Min, Tae-Su Kim, Hyun-Woo Park, Ho-Rang Jang, Keun-Cheol Hong, Sung-Jae Kim
  • Publication number: 20040148464
    Abstract: A cache memory device for a digital signal processor (DSP) may include a cache memory for providing an instruction to a DSP core of the DSP in response to a request from the DSP core, and another cache memory for enabling a running flag signal in response to an interrupt signal received from the DSP core. The cache memory that enables the running flag may provide a given number of instructions that are different from the first provided instruction, in response to further requests for instructions from the DSP core. Additionally, the cache memory handling the given number of different instructions may disable the running flag signal and cease providing the different instructions when the given number of instructions reaches a threshold value. The above process may be iteratively repeated until there are no further instruction requests from the DSP core to be processed.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventor: Ho-Rang Jang
  • Publication number: 20040002861
    Abstract: A method and apparatus for calculating an observation probability includes a first operation unit that subtracts a mean of a first plurality of parameters of an input voice signal from a second parameter of an input voice signal, and multiplies the subtraction result to obtain a first output. The first output is squared and accumulated N times in a second operation unit to obtain a second output. A third operation unit subtracts a given weighted value from the second output to obtain a third output, and a comparator stores the third output for a comparator stores the third output in order to extract L outputs therefrom, and stores the L extracted outputs based on an order of magnitude of the extracted L outputs.
    Type: Application
    Filed: June 20, 2003
    Publication date: January 1, 2004
    Inventors: Byung-Ho Min, Tae-Su Kim, Hyun-Woo Park, Ho-Rang Jang, Keun-Cheol Hong, Sung-Jae Kim
  • Publication number: 20040002862
    Abstract: A voice recognition device including dedicated arithmetic calculating modules for arithmetic operations that are more frequently required among arithmetic operations necessary for voice recognition, an observation probability calculating device for calculating probabilities that each of the phonemes of a pre-selected word can be observed upon voice recognition, a complex Fast Fourier Transform (FFT) calculation device and method of calculating a complex FFT of complex data, a cache, and a cache controlling method are provided. The arithmetic modules interpret commands received from a receiver and perform operations indicated by the commands.
    Type: Application
    Filed: May 30, 2003
    Publication date: January 1, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-ho Kim, Hyun-woo Park, Tae-su Kim, Mi-jung Noh, Byung-ho Min, Ki-won Jo, Sung-hwan Jo, Seung-hwan Lee, Jin-won Jeong, Ho-rang Jang, Sun-hee Park, Keun-cheol Hong, Sung-jae Kim
  • Patent number: 6542002
    Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: April 1, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-rang Jang, Ki-won Jo
  • Patent number: 6505288
    Abstract: A digital signal processor capable of performing matrix operations, by which it is possible to use a method of matrix representation for the instruction level of the digital signal processor in order to effectively process a large amount of data, is provided.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: January 7, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-rang Jang, Hyun-woo Park, Jin-ckuc Cho