Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: Provided is radio frequency integrated circuit(RFIC).

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: A method and apparatus for calculating an observation probability includes a first operation unit that subtracts a mean of a first plurality of parameters of an input voice signal from a second parameter of an input voice signal, and multiplies the subtraction result to obtain a first output. The first output is squared and accumulated N times in a second operation unit to obtain a second output. A third operation unit subtracts a given weighted value from the second output to obtain a third output, and a comparator stores the third output for a comparator stores the third output in order to extract L outputs therefrom, and stores the L extracted outputs based on an order of magnitude of the extracted L outputs.

Abstract: A cache memory device for a digital signal processor (DSP) may include a cache memory for providing an instruction to a DSP core of the DSP in response to a request from the DSP core, and another cache memory for enabling a running flag signal in response to an interrupt signal received from the DSP core. The cache memory that enables the running flag may provide a given number of instructions that are different from the first provided instruction, in response to further requests for instructions from the DSP core. Additionally, the cache memory handling the given number of different instructions may disable the running flag signal and cease providing the different instructions when the given number of instructions reaches a threshold value. The above process may be iteratively repeated until there are no further instruction requests from the DSP core to be processed.

Abstract: A method and apparatus for calculating an observation probability includes a first operation unit that subtracts a mean of a first plurality of parameters of an input voice signal from a second parameter of an input voice signal, and multiplies the subtraction result to obtain a first output. The first output is squared and accumulated N times in a second operation unit to obtain a second output. A third operation unit subtracts a given weighted value from the second output to obtain a third output, and a comparator stores the third output for a comparator stores the third output in order to extract L outputs therefrom, and stores the L extracted outputs based on an order of magnitude of the extracted L outputs.

Abstract: A voice recognition device including dedicated arithmetic calculating modules for arithmetic operations that are more frequently required among arithmetic operations necessary for voice recognition, an observation probability calculating device for calculating probabilities that each of the phonemes of a pre-selected word can be observed upon voice recognition, a complex Fast Fourier Transform (FFT) calculation device and method of calculating a complex FFT of complex data, a cache, and a cache controlling method are provided. The arithmetic modules interpret commands received from a receiver and perform operations indicated by the commands.