Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.

Abstract: A digital signal processor capable of performing matrix operations, by which it is possible to use a method of matrix representation for the instruction level of the digital signal processor in order to effectively process a large amount of data, is provided.

Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.

Abstract: A digital signal processor includes an execution unit separated into an arithmetic unit, a multiplier unit, a logic unit, a shift unit and a log unit, to implement CCITT G721 ADPCM algorithm with a relatively small size, which reduces the system cost. Also, since the digital signal processor primarily takes into consideration of low power consumption, it is applicable to a mobile communication system. Also, the digital signal processor is capable of implementing easily other ADPCM rates and algorithms as well as the ADPCM algorithm by modifying only the program of an instruction ROM.

Abstract: A digital data recovering apparatus which includes an edge detector, a threshold comparator, a position address generator, a position memory, a maximum position detector, a new position generator and a recovered data detector. The digital data recovering apparatus ensures that the desired data and clock reference can be recovered by exactly synchronizing the input data on a communication path, including a noise and/or jitter component.