Patents by Inventor Ho-seop Kim

Ho-seop Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10397760
    Abstract: A user terminal device and a method for providing a web service thereof are provided. The web service providing method of a user terminal device includes connecting to a web server which provides a web service, setting at least one of a plurality of web services provided by the web server based on a user command, and transmitting information on an address of the set web service to an external IoT device.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Park, Hong-uk Woo, Ming Jin, Yong-jin Kim, Jong-won Kim, Ho-yong Jung, Hun-seop Jeong
  • Patent number: 10329416
    Abstract: The present disclosure relates to a thermoplastic resin composition and a molded article manufactured from the same. More particularly, the present disclosure relates to a thermoplastic resin composition including (A) a graft copolymer prepared by graft-copolymerizing a conjugated diene rubber, a (meth)acrylic acid alkyl ester compound, a methylene butyrolactone compound, and an aromatic vinyl compound; and (B) a copolymer prepared by copolymerizing a (meth)acrylic acid alkyl ester compound, an aromatic vinyl compound, and a vinyl cyanide compound, and a molded article manufactured from the thermoplastic resin composition. In accordance with the present disclosure, a thermoplastic resin composition having superior heat resistance and transparency and a molded article manufactured from the same are provided.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 25, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Won Seok Lee, Jeong Su Choi, Keun Hoon Yoo, Seok Goo Jang, Roo Da Lee, Sang Hoo Park, Ho Hoon Kim, Hyung Seop Shim
  • Patent number: 10316179
    Abstract: The present invention relates to a transparent thermoplastic resin. More particularly, the present invention relates to a transparent thermoplastic resin, including a random copolymerization block prepared by polymerizing 50 to 80% by weight of an aromatic vinyl compound, 10 to 30% by weight of a vinyl cyanide compound, and 0 to 15% by weight of (meth)acrylic acid alkyl ester; and an aromatic vinyl compound block prepared by polymerizing 1 to 10% by weight of an aromatic vinyl compound, a transparent thermoplastic resin composition including the transparent thermoplastic resin, and methods of preparing the aromatic vinyl compound and transparent thermoplastic resin.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Roo Da Lee, Jeong Su Choi, Keun Hoon Yoo, Won Seok Lee, Seok Goo Jang, Sang Hoo Park, Ho Hoon Kim, Hyung Seop Shim
  • Publication number: 20180060049
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
  • Patent number: 9672019
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 9619750
    Abstract: An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: April 11, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ho-Seop Kim, Robert S. Chappell, Choon Yip Soo
  • Patent number: 9348766
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Adi Basel, Gur Hildesheim, Shlomo Raikin, Robert Chappell, Ho-Seop Kim, Rohit Bhatia
  • Patent number: 9292294
    Abstract: Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Muawya M. Al-Otoom, Paul Caprioli, Ryan Carlson, Ho-Seop Kim, Omar Shaikh
  • Patent number: 9244827
    Abstract: A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventors: Ho-Seop Kim, Robert S. Chappell, Choon Y. Soo, Srikanth T. Srinivasan
  • Publication number: 20150089186
    Abstract: A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: Ho-Seop Kim, Robert S. Chappell, Choon Y. Soo, Srikanth T. Srinivasan
  • Patent number: 8935678
    Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Cheng Wang, Ho-Seop Kim
  • Publication number: 20150006452
    Abstract: An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Ho-Seop KIM, Robert S. CHAPPELL, Choon Yip SOO
  • Publication number: 20140215161
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.
    Type: Application
    Filed: December 21, 2011
    Publication date: July 31, 2014
    Inventors: Adi Basel, Gur Hildeshem, Shlomo Raikin, Robert Chappell, Ho-Seop Kim, Rohit Bhatia
  • Patent number: 8700110
    Abstract: A rolled superconducting article includes: a cylindrical bobbin having a post in a cylindrical shape; a superconducting strip wound on the cylindrical bobbin in a rolled shape with a predetermined tension applied, wherein the superconducting strip is formed of a superconducting thin film, which is coated with a metal coating layer on a facing surface of the superconducting thin film, and a stabilizing substrate wound on the superconducting strip, wherein the stabilizing substrate is coated with a metal coating layer on a facing surface of the stabilizing substrate; an anti-bonding substrate wound on an outer surface of the stabilizing substrate with a predetermined tension applied; wherein the superconducting thin film is thermally adhered to the stabilizing substrate by heat-treating the rolled superconducting strip with the anti-bonding substrate wound therearound.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 15, 2014
    Assignee: Korea Electrotechnology Research Institute
    Inventors: Hong Soo Ha, Sang Soo Oh, Dong Woo Ha, Kyu Jung Song, Rock Kil Ko, Ho Seop Kim
  • Publication number: 20140089271
    Abstract: Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Muawya M. AL-OTOOM, Paul CAPRIOLI, Ryan CARLSON, Ho-Seop KIM, Omar SHAIKH
  • Patent number: 8321840
    Abstract: Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Vijayanand Nagarajan, Ho-Seop Kim, Youfeng Wu, Rajiv Gupta
  • Publication number: 20120198426
    Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Inventors: Youfeng Wu, Cheng Wang, Ho-Seop Kim
  • Patent number: 8156480
    Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Cheng Wang, Ho-Seop Kim
  • Patent number: 8146106
    Abstract: Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Ho-Seop Kim, Mauricio Breternitz, Jr., Youfeng Wu
  • Patent number: 8026197
    Abstract: A method and apparatus for manufacturing superconducting tape through an integrated process, including the steps of: heat-treating a substrate wound on a drum in a reaction chamber; continuously depositing components, constituting a buffer layer, a superconducting layer, a contact resistance layer, and a protective layer of the superconducting tape, which are supplied from a deposition chamber, on the substrate; and heat-treating the substrate deposited with the components.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: September 27, 2011
    Assignee: Korea Electrotechnology Research Institute
    Inventors: Ho Seop Kim, Sang Soo Oh, Hong Soo Ha, Kyu Jung Song, Dong Woo Ha, Rock Kil Ko