Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.

Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.

Abstract: Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

Abstract: A method and apparatus for manufacturing superconducting tape through an integrated process, including the steps of: heat-treating a substrate wound on a drum in a reaction chamber; continuously depositing components, constituting a buffer layer, a superconducting layer, a contact resistance layer, and a protective layer of the superconducting tape, which are supplied from a deposition chamber, on the substrate; and heat-treating the substrate deposited with the components.

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract: Disclosed herein is a high temperature superconducting film and an apparatus for fabricating a high temperature superconducting film in a vacuum chamber through auxiliary cluster beam spraying using an evaporation method, wherein a high temperature superconducting material is deposited on a substrate in a vapor state by evaporating the high temperature superconducting material, and at the same time, a cluster beam material is formed into gas atoms by heating the cluster beam material charged in a material housing, and the formed gas atoms pass through a nozzle of an inlet of the material housing and then are sprayed and grown on the substrate in the form of the cluster beam, thereby forming pinning centers in the high temperature superconducting film.

Abstract: Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

Abstract: Disclosed herein is a method of fabricating a high temperature superconducting film in a vacuum chamber through auxiliary cluster beam spraying using an evaporation method, wherein a high temperature superconducting material is deposited on a substrate in a vapor state by evaporating the high temperature superconducting material, and at the same time, a cluster beam material is formed into gas atoms by heating the cluster beam material charged in a housing, and the formed gas atoms pass through a nozzle of an inlet of the housing and then are sprayed and grown on the substrate in the form of the cluster beam, thereby forming pinning centers in the high temperature superconducting film.

Abstract: A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

Abstract: A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.

Abstract: Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

Abstract: Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.

Abstract: Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.

Abstract: Disclosed herein is a method of fabricating a high temperature superconducting film in a vacuum chamber through auxiliary cluster beam spraying using an evaporation method, wherein a high temperature superconducting material is deposited on a substrate in a vapor state by evaporating the high temperature superconducting material, and at the same time, a cluster beam material is formed into gas atoms by heating the cluster beam material charged in a housing, and the formed gas atoms pass through a nozzle of an inlet of the housing and then are sprayed and grown on the substrate in the form of the cluster beam, thereby forming pinning centers in the high temperature superconducting film.

Abstract: In one embodiment, the present invention includes a method for instrumenting a code block with code to perform dynamic information flow tracking. Then during execution, it may be determined whether a pattern of input data to the code block has been previously received by the code block. If so, the code block may be executed, otherwise the instrumented code block may be executed. Other embodiments are described and claimed.

Abstract: A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.

Abstract: A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

Abstract: A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller. The interrupt controller for performing an interrupt bus arbitration includes an interrupt bus arbiter. The interrupt bus arbiter has N number, e.g., 8 of arbitration cells, wherein each cell simultaneously receives a corresponding bit of the arbitration information, lower bits of the corresponding bit and corresponding lower bits of the wired-ORed interrupt bus data to generate an interrupt bus gain signal when the corresponding bits represent one logic state and the lower bits represent the other logic state; and a decision circuit connected to the arbitration cells for generating an interrupt bus gain decision signal when the interrupt bus gain signal is received.