Patents by Inventor Ho Suh

Ho Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040136464
    Abstract: A method for generating a preamble sequence for decreasing a peak-to-average power ratio (PAPR) through at least two antennas in an orthogonal frequency division multiplexing (OFDM) communication system. The method comprises generating a first preamble sequence in which odd data of the preamble sequence becomes null data and even data of the preamble sequence becomes data, the first preamble sequence being adapted to be transmitted via one of the two antennas; and generating a second preamble sequence in which even data of the preamble sequence becomes null data and odd data of the preamble sequence becomes data, the second preamble sequence being adapted to be transmitted via another one of the two antennas.
    Type: Application
    Filed: December 1, 2003
    Publication date: July 15, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Ho Suh, Chan-Byoung Chae, Ho-Kyu Choi, Jung-Min Ro, Pan-Yuh Joo
  • Publication number: 20040114504
    Abstract: A method and apparatus for generating a preamble sequence in an orthogonal frequency division multiplexing (OFDM) communication system having m subcarriers in a frequency domain. The method comprises generating a preamble sequence of length n that is mapped to n subcarriers on a one-to-one basis, where n is less than m; and assigning components constituting the preamble sequence to the n subcarriers among the m subcarriers on a one-to-one mapping basis, assigning null data to the remaining subcarriers excluding the n subcarriers from the m subcarriers, and then IFFT (Inverse Fast Fourier Transform)-transforming the assigned result into time-domain data.
    Type: Application
    Filed: October 23, 2003
    Publication date: June 17, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Kwon Jung, Chang-Ho Suh, Pan-Yuh Joo, Dong-Seek Park, Ho-Kyu Choi
  • Publication number: 20040109405
    Abstract: A method for generating a preamble sequence in an orthogonal frequency division multiplexing (OFDM) communication system having A subcarriers in a frequency domain. The method comprises generating a length-M×N preamble sequence, where M×N is less than A, by using a length-N Golay complementary sequence and a length-M Golay complementary sequence; and assigning elements constituting the preamble sequence to M×N subcarriers among the A subcarriers on a one-to-one mapping basis, assigning null data to the remaining subcarriers excluding the M×N subcarriers from the A subcarriers, and then IFFT-transforming the assigned result into time-domain data.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 10, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Ho Suh, Chan-Byoung Chae, Ho-Kyu Choi, Jung-Min Ro, Pan-Yuh Joo
  • Publication number: 20040066740
    Abstract: Disclosed is an apparatus and a method for generating a preamble sequence in an orthogonal frequency division multiplexing (OFDM) communication system having m subcarriers in a frequency domain. The method comprises grouping the m subcarriers by n subcarriers, where n is less than m, so as to generate p subchannels; and assigning null data to subcarriers except the n subcarriers assigned to the subchannels, assigning data of a given sequence to at least one subchannel selected from the p subchannels, assigning null data to subchannels not selected from the p subchannels, and thereafter performing inverse fast Fourier transform (IFFT) for transforming the data into time-domain data.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 8, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Ho Suh, Dae-Kwon Jung, Pan-Yuh Joo, FengMing Cao, Hai Wang, Jun Chen
  • Patent number: 6674686
    Abstract: Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: January 6, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Noh, Young-Ho Suh
  • Publication number: 20030172275
    Abstract: The present invention relates to a protection of copyrights of digital data, and more particularly, to a real-time blind watermarking method using quantization, in which a watermark information for representing ownership is embedded in a digital image, video or the like so as not to be visually or aurally discriminated and is extracted after various attacks such as edit or the like, and which can be used in all compression ways. The real-time video watermarking system is a blind method and is simple. In order to perform DCT with respect to an original frame and enhance the robustness, the watermark is embedded in a low frequency component. Further, since the DCT is not performed with respect to all blocks, the invention has a rapid operation speed regardless of the size of the video frame.
    Type: Application
    Filed: May 20, 2002
    Publication date: September 11, 2003
    Inventors: Seung Wook Lee, Jin Ho Kim, Won Young Yoo, Young Ho Suh
  • Patent number: 6618299
    Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: September 9, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Young-Ho Suh
  • Publication number: 20030099373
    Abstract: An apparatus and method for embedding and extracting digital watermarks using a blind mode based on wavelet transform which is robust to external attacks while being capable of minimizing a degradation in picture quality caused by embedding of the watermarks. In accordance with the invention, watermarks protection of the copyright for desired data are embedded in DC component domains of wavelet-transformed domains. In accordance with the invention, embedding of watermarks in a target image corresponding to a target domain in which the watermarks are to be embedded, is achieved by generating a data stream of the watermarks in accordance with a key value selected by the user, generating index information representing positions where the watermarks are to be embedded, in accordance with a key value selected by the ser, and reflecting the watermark data stream on data values of pixels in the target image at the positions based on the index information.
    Type: Application
    Filed: December 31, 2001
    Publication date: May 29, 2003
    Inventors: Sanghyun Joo, Yong-Seok Seo, Young Ho Suh, Weon Geun Oh
  • Publication number: 20030095682
    Abstract: An apparatus and method for embedding and extracting digital watermarks based on wavelets which is robust to external attacks while being capable of minimizing a degradation in picture quality caused by embedding of the watermarks. The embedded watermarks embedded in DC component domains of wavelet-transformed domains can be robust to external attacks such as compression. The high-frequency dependency of pixels in a DC component domain determined as a target domain, in which watermarks are to be embedded, is calculated, in order to embed the watermarks in the target domain in the order of pixels having a higher high-frequency dependency. Accordingly, there is an advantage in that it is possible to minimize a degradation in picture quality caused by the embedding of watermarks in the DC component domain.
    Type: Application
    Filed: March 18, 2002
    Publication date: May 22, 2003
    Inventors: Sanghyun Joo, Yong-Seok Seo, Young Ho Suh
  • Patent number: 6501306
    Abstract: A data output circuit for a semiconductor device with a level shifter and a method for outputting data using the same.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 31, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Hwan Kim, Young-Ho Suh
  • Patent number: 6490206
    Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: December 3, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kook-Hwan Kwon, Young-Ho Suh
  • Publication number: 20020154565
    Abstract: Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. In one aspect, read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) in a separate input and output architecture wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time. In another aspect, read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4) in a separate input and output architecture, wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time.
    Type: Application
    Filed: November 9, 2001
    Publication date: October 24, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Noh, Young-Ho Suh
  • Publication number: 20020086449
    Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.
    Type: Application
    Filed: September 5, 2001
    Publication date: July 4, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Young-Ho Suh
  • Publication number: 20020085004
    Abstract: An algebraic blending method accomplishes continuity of two n-the order curves or curved surface patch by generating a new control point of boundary by using a simple algebraic blending method in modeling a free curves/curved surface constructed by a B-spline. At a first step, a B-spline curved surface patch is obtained by using universal parametrization. At a second step, two adjacent patch to be connected with continuity is selected among the patch obtained at the first step. At a third step, at least one control point of a large patch is obtained by obtaining control points of the selected two curved surfaces and blending superposed control points. At a final step, a B-spline curved surface patch is obtained by using the obtained control points of the large patch and the two patch of the original model is replaced with the B-spline curved surface patch.
    Type: Application
    Filed: August 27, 2001
    Publication date: July 4, 2002
    Inventors: Choong-Gyoo Lim, Young-Ho Suh, Weon-Geun Oh
  • Publication number: 20020048196
    Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.
    Type: Application
    Filed: September 20, 2001
    Publication date: April 25, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kook-Hwan Kwon, Young-Ho Suh
  • Patent number: 6310504
    Abstract: A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: October 30, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Suh, Jin-Ho Lee
  • Patent number: 6271705
    Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: August 7, 2001
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Young-Ho Suh, Choong-Keun Kwak, Sang-Jib Han
  • Patent number: 6271718
    Abstract: The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: August 7, 2001
    Assignee: Samsung Electronics
    Inventors: Kyo-Min Sohn, Young-Ho Suh
  • Patent number: 6198650
    Abstract: It is disclosed a semiconductor memory device and data output buffer thereof in which an area of a layout can be optimized.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: March 6, 2001
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Young-Ho Suh
  • Patent number: 6150873
    Abstract: The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: November 21, 2000
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Kyo-Min Sohn, Young-Ho Suh