Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Abstract: Integrated circuit memory devices include overlapping bit lines and power supply lines. The integrated circuit memory devices include a memory cell array in an integrated circuit substrate and a plurality of spaced apart bit lines on the memory cell array, extending in a first direction. A plurality of spaced apart power lines are also included on the memory cell array, extending in the first direction, and on at least one of the plurality of bit lines. The overlapping bit lines and power supply lines are insulated from one another, for example by providing these lines in first and second patterned conductive layers. Accordingly, higher density integrated circuit devices may be provided while allowing high speed operation and effective power supply voltage distribution.

Abstract: An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.

Abstract: In semiconductor memory devices, failed memory cells are problematic because they draw excessive standby currents. To repair such devices before packaging, the failed memory cell columns are replaced by redundant columns. To ensure that a replaced column having a failed cell does not draw excessive standby current, the invention provides for turning off the precharge circuit transistor pair that otherwise would supply precharge current to the bit line pair in the defective column, and also turning off the cell power line circuit that otherwise would supply current along a cell power line to the cell power nodes in the defective column of the memory array.

Abstract: A data output circuit of a semiconductor memory device matches an equalizing level of voltages at data lines in a pair with a logic threshold voltage of data output buffers. The data output circuit having an equalizing transistor connected between first and second nodes connected to the outputs of a sense amplifier, includes a threshold voltage control circuit disposed between the sense amplifier and the data output buffers for allowing a threshold voltage of the data output buffers to match with the equalizing level of the voltages at the first and second nodes. The threshold voltage control circuit has the same structure and characteristics as that of the output buffers, so as to ensure that the logic threshold voltage of the data output buffers matches with the equalizing level of the voltages at the first and second nodes.

Abstract: A semiconductor memory device includes bit line pair precharge circuits for precharging bit lines in a memory cell array. The semiconductor memory device includes a number of memory cells each sharing a pair of bit lines, each bit line pair together with corresponding memory cells constituting the memory cell array. The memory device further includes a first bit line precharge circuit coupled to a first position along each bit line pair for precharging the respective bit lines under the control of a block selection signal and a write enable signal. A second bit line precharge circuit is connected at a second position along the bit line pair for precharging the respective bit line pair under the control of the write enable signal. A positional distance between the first position and the second position being such as to optimally reduce a bit line precharge time and a write recovery time associated with each bit line pair in the memory cell array.

Abstract: A circuit for generating an internal source voltage which is applied to the memory elements of a semiconductor device. The circuit includes a reference voltage generating circuit for generating a reference voltage, a comparator for comparing the internal source voltage with the reference voltage, a driver for driving an external source voltage into the internal source voltage under the control of the comparator, and a low reference voltage generating circuit for generating a control signal to fully turn on the driver when the voltage level of the external source voltage is lower than the voltage level of the reference voltage generating circuit and which prevents the driver from receiving the output signal of the comparator so as to apply the external source voltage to the memory element of the memory device.