Patents by Inventor Ho Uk Song
Ho Uk Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11646072Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.Type: GrantFiled: September 21, 2021Date of Patent: May 9, 2023Assignee: SK hynix Inc.Inventors: Hyun Seung Kim, Ho Uk Song, Tae Kyun Shin, Min Jun Choi, Duck Hwa Hong
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Publication number: 20220406367Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.Type: ApplicationFiled: September 21, 2021Publication date: December 22, 2022Applicant: SK hynix Inc.Inventors: Hyun Seung KIM, Ho Uk SONG, Tae Kyun SHIN, Min Jun CHOI, Duck Hwa HONG
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Patent number: 10763181Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.Type: GrantFiled: September 13, 2018Date of Patent: September 1, 2020Assignee: SK hynix Inc.Inventors: Hee-Jin Byun, Ho-Uk Song, Sun-Young Hwang
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Publication number: 20190164856Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.Type: ApplicationFiled: September 13, 2018Publication date: May 30, 2019Inventors: Hee-Jin BYUN, Ho-Uk SONG, Sun-Young HWANG
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Patent number: 9767885Abstract: A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.Type: GrantFiled: January 13, 2017Date of Patent: September 19, 2017Assignee: SK hynix Inc.Inventors: A Ram Rim, Ho Uk Song
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Publication number: 20170133079Abstract: A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.Type: ApplicationFiled: January 13, 2017Publication date: May 11, 2017Inventors: A Ram RIM, Ho Uk SONG
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Patent number: 9627020Abstract: A semiconductor device may be provided. The semiconductor device may include a reference mat including a reference bit line and a reference word line, the reference mat, located adjacent to a normal mat, and the reference mat configured such that a capacitance of the reference bit line is adjusted based on a signal of the reference word line. The semiconductor device may include a drive controller configured to drive the signal of the reference word line with a drive voltage based on a boosting voltage, the drive voltage having a lower voltage level than the boosting voltage.Type: GrantFiled: May 26, 2016Date of Patent: April 18, 2017Assignee: SK HYNIX INC.Inventor: Ho Uk Song
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Patent number: 9583173Abstract: A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.Type: GrantFiled: July 24, 2015Date of Patent: February 28, 2017Assignee: SK HYNIX INC.Inventors: A Ram Rim, Ho Uk Song
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Patent number: 9543837Abstract: An apparatus for adjusting an internal voltage includes a device characteristic detection circuit which detects a device characteristic, compares the device characteristic with an external clock, and generates a comparison signal, and an internal voltage adjustment circuit which receives an adjustment code generated based on the comparison signal, adjusts a level of an internal voltage, and generates a level-adjusted internal voltage.Type: GrantFiled: January 9, 2015Date of Patent: January 10, 2017Assignee: SK HYNIX INC.Inventors: Ho Uk Song, A Ram Rim
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Patent number: 9502081Abstract: An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.Type: GrantFiled: May 28, 2015Date of Patent: November 22, 2016Assignee: SK HYNIX INC.Inventors: Ho Uk Song, A Ram Rim
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Publication number: 20160307616Abstract: A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.Type: ApplicationFiled: July 24, 2015Publication date: October 20, 2016Inventors: A Ram RIM, Ho Uk SONG
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Publication number: 20160254034Abstract: An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.Type: ApplicationFiled: May 28, 2015Publication date: September 1, 2016Inventors: Ho Uk SONG, A Ram RIM
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Patent number: 9331697Abstract: An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven.Type: GrantFiled: November 19, 2013Date of Patent: May 3, 2016Assignee: SK hynix Inc.Inventor: Ho Uk Song
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Patent number: 9324408Abstract: A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, the first power control signal having an enablement period that may be controlled in response to a temperature signal having a cycle time. The cycle time may be controlled according to a mode signal and an internal temperature. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage.Type: GrantFiled: September 30, 2014Date of Patent: April 26, 2016Assignee: SK hynix Inc.Inventors: A Ram Rim, Ho Uk Song
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Publication number: 20160056716Abstract: An apparatus for adjusting an internal voltage includes a device characteristic detection circuit which detects a device characteristic, compares the device characteristic with an external clock, and generates a comparison signal, and an internal voltage adjustment circuit which receives an adjustment code generated based on the comparison signal, adjusts a level of an internal voltage, and generates a level-adjusted internal voltage.Type: ApplicationFiled: January 9, 2015Publication date: February 25, 2016Inventors: Ho Uk SONG, A Ram RIM
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Publication number: 20150348611Abstract: A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, the first power control signal having an enablement period that may be controlled in response to a temperature signal having a cycle time. The cycle time may be controlled according to a mode signal and an internal temperature. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage.Type: ApplicationFiled: September 30, 2014Publication date: December 3, 2015Inventors: A Ram RIM, Ho Uk SONG
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Publication number: 20150338456Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.Type: ApplicationFiled: August 3, 2015Publication date: November 26, 2015Inventors: Young Suk SEO, Ho Uk SONG, Jun Hyun CHUN, Tae Jin KANG
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Patent number: 9194907Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.Type: GrantFiled: August 3, 2015Date of Patent: November 24, 2015Assignee: SK Hynix Inc.Inventors: Young Suk Seo, Ho Uk Song, Jun Hyun Chun, Tae Jin Kang
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Patent number: 9128145Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.Type: GrantFiled: March 18, 2013Date of Patent: September 8, 2015Assignee: SK Hynix Inc.Inventors: Young Suk Seo, Ho Uk Song, Jun Hyun Chun, Tae Jin Kang
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Publication number: 20150213906Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.Type: ApplicationFiled: April 13, 2015Publication date: July 30, 2015Inventors: Joo-Hyeon LEE, Jun-Hyun CHUN, Ho-Uk SONG