Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to Nth programmable storage cell groups is performed or skipped based on the determined result.

Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.

Abstract: An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven.

Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.

Abstract: A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin.

Abstract: A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin.

Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: A semiconductor memory device includes: input/output line coupled to a first bit line of a first mat including a plurality of memory cells; a second input/output line coupled to a second bit line of a second mat including a plurality of memory cells; and a switching unit configured to couple the first input/output line and the second input/output line in response to a precharge signal.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: An internal voltage generation circuit includes a first enable signal generator configured to delay an active signal to generate a first enable signal, a comparison signal generator configured to compare the internal voltage with an internal reference voltage to generate a comparison signal, a pulse signal generator configured to receive the first enable signal and to generate a pulse signal, a transmission device configured to buffer and transfer the comparison signal as a pull-down signal, and a drive device configured to drive the driving signal to the first level in response to the pull-down signal.

Abstract: A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of the peripheral circuit voltage in response to a column path command.

Abstract: A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A periodic signal generating circuit which is dependent upon temperature for establishing a temperature independent refresh frequency is presented. The periodic signal generating circuit includes a reference voltage generating unit and a periodic signal generating unit. The reference voltage generating unit produces a reference voltage which exhibits a variable voltage level in response to temperature. The periodic signal generating unit produces a periodic signal in response to a set voltage to determine the reference voltage and an oscillation period, wherein a transition timing of the set voltage is controlled by the reference voltage. As a result the periodic signal has a relatively constant period which can be produced regardless of the temperature variation.

Abstract: A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level.

Abstract: An internal voltage generation circuit includes a first enable signal generator configured to delay an active signal to generate a first enable signal, a comparison signal generator configured to compare the internal voltage with an internal reference voltage to generate a comparison signal, a pulse signal generator configured to receive the first enable signal and to generate a pulse signal, a transmission device configured to buffer and transfer the comparison signal as a pull-down signal, and a drive device configured to drive the driving signal to the first level in response to the pull-down signal.

Abstract: A periodic signal generating circuit which is dependent upon temperature for establishing a temperature independent refresh frequency is presented. The periodic signal generating circuit includes a reference voltage generating unit and a periodic signal generating unit. The reference voltage generating unit produces a reference voltage which exhibits a variable voltage level in response to temperature. The periodic signal generating unit produces a periodic signal in response to a set voltage to determine the reference voltage and an oscillation period, wherein a transition timing of the set voltage is controlled by the reference voltage. As a result the periodic signal has a relatively constant period which can be produced regardless of the temperature variation.