Patents by Inventor Ho Yi

Ho Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070246811
    Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 25, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Ho-Yi Tsai, Han-Ping Pu, Cheng-Hsu Hsiao
  • Patent number: 7271483
    Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 18, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Ren Lin, Chien-Ping Huang, Ho-Yi Tsai, Cheng-Hsu Hsiao
  • Publication number: 20070202633
    Abstract: A semiconductor package and a method for fabricating the same are provided. The method includes providing a substrate having recognition points and a heat sink having openings, and placing the heat sink on the substrate with the recognition points being exposed through the openings; using a checking system to inspect the recognition points through the openings so as to ensure that the heat sink is placed at a predetermined position on the substrate; and attaching the heat sink to the substrate via an adhesive. By the above semiconductor package and method, there is no need to form positioning holes in the substrate such that any adverse effect on the circuit layout and reliability of the semiconductor package is avoided, and any positional shifting of the heat sink relative to the substrate can be determined in a real time manner.
    Type: Application
    Filed: January 9, 2007
    Publication date: August 30, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Tsung Tseng, Fang-Lin Tsai, Ho-Yi Tsai, Cheng-Hsu Hsiao, Chih-Ming Huang
  • Publication number: 20070164084
    Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 19, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Ho-Yi Tsai, Wen-Tsung Tseng, Chih-Ming Huang
  • Publication number: 20070145561
    Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 28, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Ho-Yi Tsai, Chih-Ming Huang, Chien-Ping Huang
  • Publication number: 20070138632
    Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 21, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Ho-Yi Tsai, Chih-Ming Huang, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20070141761
    Abstract: A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packa
    Type: Application
    Filed: February 6, 2007
    Publication date: June 21, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20070128539
    Abstract: In a method of forming a pattern using a composition for removing photoresist, a layer is formed on a substrate, and then a photoresist pattern is formed on the layer. A portion of the layer exposed by the photoresist pattern is etched using the photoresist pattern as an etching mask to form the pattern on the substrate. Then, the photoresist pattern is removed using the composition including hydroxylamine, an alkanolamine-based compound, a morpholine-based compound, a polar solvent, a corrosion preventing agent, and water. The composition may effectively remove a photoresist pattern and etched residues without damaging the substrate and/or the pattern including metal, nitride, oxide and/or metal nitride.
    Type: Application
    Filed: September 21, 2006
    Publication date: June 7, 2007
    Inventors: Jun-Ing KIL, Sok-Ho Yi, Kyong-Hee Kim, Hee Seo, Bon-Wang Koo, Min-Young Kim
  • Publication number: 20070054484
    Abstract: A method for positioning a semiconductor component is disclosed. The method includes providing the semiconductor component and a carrier, the carrier having a plurality of openings, a protruded portion being provided at each corner position of each of the openings and extended toward a center of the opening, a distance between two diagonal protruded portions of the opening being slightly larger than that between two diagonal corners of the semiconductor component; and positioning the semiconductor component in the openings of the carrier via the protruded portions provided at each corner position of each of the openings.
    Type: Application
    Filed: October 26, 2006
    Publication date: March 8, 2007
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang
  • Patent number: 7180183
    Abstract: A semiconductor device with reinforced under-support structure and a method for fabricating the semiconductor device are provided, which can be used in the packaging of an MPBGA/TFBGA (Multi-Package Ball Grid Array & Thin Fine-pitch Ball Grid Array) module to help reinforce the TFBGA under-support structure therein. The proposed chip-packaging method is characterized by the provision of large-area solder pads at the corners of a solder-pad array used for TFBGA attaching application, in order to form solder bumps of a large cross section and volume during reflow process to help reinforce the TFBGA under-package structure. This feature can reinforce the TFBGA under-package structure without having to use flip-chip underfill technology, and without having to use extra large type solder balls and arrange pads into different pitches as in the prior art.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: February 20, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ho-Yi Tsai, Chin-Ming Shih, Ying-Ren Lin
  • Publication number: 20070029683
    Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.
    Type: Application
    Filed: October 12, 2006
    Publication date: February 8, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ho-Yi Tsai, Chien-Ping Huang
  • Patent number: 7173828
    Abstract: A ground pad structure for preventing solder extrusion and a semiconductor package having the ground pad structure are disclosed, wherein the ground pad structure has the ground pads located along the circumference of its ground plane be formed in a non-solder mask defined manner. Accordingly, a good grounding quality is maintained, and the occurrence of the electrical bridging among the adjacent conductive traces can be avoided as the extrusion of the molten solder bumps from the ground pads located along the ground pad structure's circumference toward their adjacent conductive traces is effectively prevented.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: February 6, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Ren Lin, Chih-Ming Huang, Ho-Yi Tsai
  • Patent number: 7164210
    Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: January 16, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ho-Yi Tsai, Chien-Ping Huang
  • Publication number: 20060292741
    Abstract: A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 28, 2006
    Inventors: Wen-Tsung Tseng, Ho-Yi Tsai, Chien-Ping Huang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20060273452
    Abstract: A semiconductor package and a fabrication method thereof are provided. During a molding process, a substrate mounted with a chip is placed in a mold having a molding cavity, wherein the molding cavity is sized larger than the predetermined size of the semiconductor package, and a portion of the mold for clamping the substrate is located outside a circuit layout area of the substrate. Thereby, an encapsulant subsequently formed for encapsulating the chip is sized larger than the predetermined size of the semiconductor package. Then, a singulation process is performed to remove portions of the encapsulant and portions of the substrate unit larger in size than the predetermined size of the semiconductor package, such that damage to circuits of the substrate can be prevented. Further, during the fabrication processes, a heat sink may be mounted on the chip to form a thermally enhanced semiconductor package.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 7, 2006
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ho-Yi Tsai, Chien-Ping Huang, Hung-Min Shun
  • Patent number: 7129119
    Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: October 31, 2006
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang
  • Publication number: 20060091527
    Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.
    Type: Application
    Filed: December 29, 2004
    Publication date: May 4, 2006
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ho-Yi Tsai, Chien-Ping Huang
  • Publication number: 20060051954
    Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.
    Type: Application
    Filed: December 29, 2004
    Publication date: March 9, 2006
    Applicant: Siliconware Precision Industries Co, Ltd.
    Inventors: Ying-Ren Lin, Chien-Ping Huang, Ho-Yi Tsai, Cheng-Hsu Hsiao
  • Publication number: 20050287713
    Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.
    Type: Application
    Filed: February 1, 2005
    Publication date: December 29, 2005
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang
  • Publication number: 20050287707
    Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.
    Type: Application
    Filed: April 27, 2005
    Publication date: December 29, 2005
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao