Patents by Inventor Hoe-Ku Jung

Hoe-Ku Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8633392
    Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 21, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shuhichi Okabe, Myung-Sam Kang, Jung-Hyun Park, Hoe-Ku Jung, Jeong-Woo Park, Ji-Eun Kim
  • Patent number: 8418355
    Abstract: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: April 16, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang-Duck Kim, Jung-Hyun Park, Hoe-Ku Jung, Jong-Gyu Choi, Ji-Eun Kim, Jeong-Woo Park
  • Publication number: 20120111607
    Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Shuhichi OKABE, Myung-Sam Kang, Jung-Hyun Park, Hoe-Ku Jung, Jeong-Woo Park, Ji-Eun Kim
  • Patent number: 8124880
    Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: February 28, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shuhichi Okabe, Myung-Sam Kang, Jung-Hyun Park, Hoe-Ku Jung, Jeong-Woo Park, Ji-Eun Kim
  • Publication number: 20110259627
    Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.
    Type: Application
    Filed: July 1, 2011
    Publication date: October 27, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
  • Publication number: 20110221074
    Abstract: A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.
    Type: Application
    Filed: May 17, 2011
    Publication date: September 15, 2011
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung-Sam Kang, Chang-Sup Ryu, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Patent number: 8003439
    Abstract: A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: August 23, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung-Sam Kang, Chang-Sup Ryu, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Patent number: 7992291
    Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 9, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
  • Patent number: 7937833
    Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: May 10, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
  • Patent number: 7858437
    Abstract: An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: December 28, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Myung-Sam Kang, Ji-Eun Kim, Jung-Hyun Park
  • Publication number: 20100255634
    Abstract: A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.
    Type: Application
    Filed: June 15, 2010
    Publication date: October 7, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung-Hyun Park, Byoung-Youl Min, Je-Gwang Yoo, Myung-Sam Kang, Hoe-Ku Jung, Ji-Eun Kim
  • Patent number: 7802358
    Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: September 28, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Myung-Sam Kang, Jung-Hyun Park
  • Publication number: 20090242238
    Abstract: A buried pattern substrate includes an insulation layer; a circuit pattern buried in the insulation layer such that a part thereof is exposed at a surface of the insulation layer; and a stud bump buried in the insulation layer such that one end portion is exposed at one surface of the insulation layer, and such that the other end portion is exposed at the other surface of the insulation layer.
    Type: Application
    Filed: June 2, 2009
    Publication date: October 1, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Shuhichi Okabe, Myung-Sam Kang, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Publication number: 20090233400
    Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.
    Type: Application
    Filed: May 22, 2009
    Publication date: September 17, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hoe-Ku Jung, Myung-Sam Kang, Jung-Hyun Park
  • Publication number: 20090206468
    Abstract: A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.
    Type: Application
    Filed: April 3, 2009
    Publication date: August 20, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung-Sam Kang, Chang-Sup Ryu, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Patent number: 7562446
    Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: July 21, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Myung-Sam Kang, Jung-Hyun Park
  • Patent number: 7550316
    Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 23, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung-Sam Kang, Chang-Sup Ryu, Jung-Hyun Park, Hoe-Ku Jung, Ji-Eun Kim
  • Patent number: 7516545
    Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: April 14, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Shuhichi Okabe, Jung Hyun Park, Hoe Ku Jung, Ji Eun Kim
  • Patent number: 7498205
    Abstract: A method for manufacturing a substrate having a cavity which includes forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master; coating a thermosetting material in the area where the cavity is to be formed; laminating a dielectric layer and a copper foil layer on the copper foil laminated master, on which the thermosetting material is coated; pressing the laminated dielectric layer and copper foil layer using a press plate, on which a protruded part is formed in an area corresponding to the area where the cavity is to be formed; forming an external circuit pattern in the upper part of the laminated dielectric layer; and dissolving the coated thermosetting material using a solvent and forming the cavity.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 3, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe Ku Jung, Myung Sam Kang, Jung Hyun Park
  • Patent number: 7494844
    Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: February 24, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Myung-Sam Kang, Jung-Hyun Park