Abstract: Disclosed is a semiconductor device comprising a first semiconductor die and a second semiconductor die on the first semiconductor die. The first semiconductor die comprises a first pad, a first dielectric pattern that surrounds a lateral surface of the first pad, and a second dielectric pattern that surrounds a lateral surface of the first dielectric pattern. The second semiconductor die comprises a second pad in contact with the first pad. The first dielectric pattern comprises a first dielectric material. The second dielectric pattern comprises a second dielectric material different from the first dielectric material. A thermal conductivity of the second dielectric material is greater than a thermal conductivity of the first dielectric material.

Abstract: A semiconductor device may include a first semiconductor die including a first pad and a first adhesive layer covering an upper portion of a side wall of the first pad, a second semiconductor die including a second pad and a second adhesive layer covering a lower portion of a side wall of the second pad, and a first protection layer between the first pad and the second adhesive layer. A mean grain size of each of the first pad and the second pad may range from 25 nm to 70 nm. The second pad may be on the first pad, a top surface of the first pad may include a portion exposed by the second pad, and the second adhesive layer may be on the exposed portion of the first pad. The protection layer may be between the exposed portion of the first pad and the second adhesive layer.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a first subsidiary integrated circuit, an upper dielectric layer that covers the first subsidiary integrated circuit, a polishing barrier layer on the upper dielectric layer, a bonding layer on the polishing barrier layer, and a substrate on the bonding layer. The upper dielectric layer and the bonding layer comprise a first material. The polishing barrier layer comprises a second material having a polishing selectivity with respect to the first material.

Abstract: A semiconductor device includes a first semiconductor chip having a first pad structure and a second semiconductor chip having a second pad structure. The first pad structure and the second pad structure are bonded to each other in a first direction. The first pad structure includes a first filling conductive film and a second filling conductive film. The first filling conductive film includes a first portion that overlaps the second filling conductive film in the first direction, and a second portion that overlaps the second filling conductive film in a second direction intersecting the first direction. A first height of the first portion in the first direction is greater than a thickness of the second portion in the second direction, and an electrical conductivity of the second filling conductive film is greater than the electrical conductivity of the first filling conductive film.

Abstract: A semiconductor device may include a first bonding pad having a first width, and a second bonding pad coupled to the first bonding pad and having a second width different from the first width, wherein the first bonding pad includes a first material, and the second bonding pad includes a second material different from the first material.

Abstract: A semiconductor package is provided.

Abstract: A method includes providing a first substrate structure including a first semiconductor substrate having first and second surfaces opposite to each other, and a first semiconductor device layer on the first surface, providing a second substrate structure including a second semiconductor substrate having third and fourth surfaces opposite to each other, and a second semiconductor device layer on the third surface, removing a portion of the second semiconductor device layer on a first edge region of the second semiconductor substrate, electrically connecting the first and second semiconductor device layers by bonding the first and second substrate structures such that the first surface faces the third surface, forming a gap-filling film that fills a portion of a gap between the first substrate structure and the first edge region, removing a portion of the first edge region and reducing the thickness of the second semiconductor substrate using a laser trimming process.

Abstract: A semiconductor device includes a substrate that comprises a first region and a second region; a first wiring structure on the first region of the substrate, wherein the first wiring structure comprises a lower bonding pad; a second wiring structure on the first wiring structure, wherein the second wiring structure comprises an upper bonding pad that contacts the lower bonding pad; a lower alignment pattern on the second region of the substrate, wherein the lower alignment pattern is spaced apart from the lower bonding pad; and an upper alignment pattern on the second region of the substrate, wherein the upper alignment pattern is spaced apart from the upper bonding pad, wherein the lower alignment pattern comprises sub-lower alignment patterns, and wherein the upper alignment pattern comprises sub-upper alignment patterns.

Abstract: A method of fabricating a semiconductor device includes forming a substrate and a wiring layer, forming a first interlayer insulating layer on the wiring layer, forming an etch stop layer covering a portion of an upper surface of the first interlayer insulating layer, forming a compensation insulating layer on the first interlayer insulating layer and the etch stop layer, planarizing the compensation insulating layer to form a compensation insulating pattern, forming a second interlayer insulating layer on the etch stop layer, and bonding the second interlayer insulating layer and a bonding wafer. The planarizing of the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

Abstract: A tube expansion method of a tubular material includes extruding a tubular material in which a hollow is formed, inserting the tubular material into a cavity of a mold corresponding to a shape of a part to be manufactured, and performing hydroforming by injecting a pressure medium into the hollow of the tubular material at a predetermined pressure or higher, wherein a tubular material extruded through the extruding step has portions with different thicknesses along the circumferential direction. Tube expansion of the tubular material with different cross-sectional sizes in one piece is possible.

Abstract: Disclosed herein are a method for real-time interactive dance education using an avatar and an apparatus therefor. In the method, the apparatus extracts a learner pose and an instructor pose from a dance video containing multiple dance learners and an instructional dance video, respectively, renders an avatar dance video based on the extracted pose of a main learner among the multiple dance learners, generates real-time multimodal dance education feedback for the main learner based on an error between the learner pose and the instructor pose, and provides the main learner with the real-time multimodal dance education feedback synchronized to the avatar dance video.

Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.

Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.

Abstract: A semiconductor package includes a first chip and a second chip disposed thereon. The first chip includes a first semiconductor substrate including first and second surfaces, a first circuit layer disposed on the first surface, a first interconnection layer disposed on the first circuit layer, the first interconnection layer including a landing pad, a second interconnection layer disposed on the second surface, and a first penetration via protruding from the second interconnection layer and penetrating the first semiconductor substrate. The second chip includes a second semiconductor substrate including third and fourth surfaces, the fourth surface being closer to the first chip than the third surface, a third interconnection layer disposed on the fourth surface, a second circuit layer disposed between the third interconnection layer and the fourth surface, and a second penetration via penetrating the second semiconductor substrate and connected to the landing pad.

Abstract: A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

Abstract: The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and the lower interlayer insulating film to form a lower trench, forming, using a sputtering process, a first lower seed film and a second lower seed film. The forming of the upper chip includes providing an upper substrate, sequentially forming an upper interlayer insulating film and a pre-upper adhesive film, etching portions of the pre-upper adhesive film and the upper interlayer insulating film to form an upper trench, forming, using the sputtering process, a first upper seed film and a second upper seed film.

Abstract: A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

Abstract: A semiconductor device includes: a substrate including a first face, on which an active area is formed, and a second face opposite to the first face; an electronic element formed on the active area; a front wiring structure disposed on the first face of the substrate and connected to the electronic element; a trench capacitor filling at least a portion of a back trench extending into the substrate from the second face of the substrate; a back wiring structure disposed on the second face of the substrate and connected to the trench capacitor; and a through-via extending through the substrate to electrically connect the electronic element and the back wiring structure to each other.

Abstract: A semiconductor device may include a lower structure including a first substrate, a first pad on the first substrate, and a first insulating layer enclosing the first pad, and an upper structure including a second substrate, a second pad on the second substrate, and a second insulating layer enclosing the second pad. Each of the first and second pads may include a first portion and a second portion on the first portion. The second portion may include the same metallic material as the first portion. The second portion of the first pad may be in contact with the second portion of the second pad, and the first insulating layer may be in contact with the second insulating layer.

Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.