Abstract: A method of controlling a link state of a communication port of a storage device according to the present inventive concepts includes setting the link state of the communication port to a link active state that can exchange data with a host, determining a holding time of a first standby state among link states of the communication port, changing the link state of the communication port to the first standby state, monitoring whether an exit event occurs during the holding time from the time when a transition to the first standby state occurs, and in response to an exit event not occurring during the holding time, changing the link state of the communication port to a second standby state. A recovery time from the first standby state to the link active state is shorter than a recovery time from the second standby state to the link active state.

Abstract: A data transferring method of a storage device is provided. The method may include transferring a first data to a first outbound area, transferring the first data sent to the first outbound area to a first area of a main memory corresponding to a first address programmed by an address translation unit, transferring a second data to a second outbound area in response to an indication that the address translation unit is to be reprogrammed, and transferring the second data sent to the second outbound area to the first outbound area.

Abstract: An auxiliary power device includes an auxiliary power source having first and second charging cells connected in series, a cell balance circuit configured to sense a charging voltage between the first and second charging cells, generate a balance voltage based on the sensed charging voltage, and applies the generated balance voltage between the first and second charging cells, and a microprocessor configured to diagnose the first and second charging cells based on the sensed charging cells and control the cell balance circuit.

Abstract: A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage.

Abstract: A storage device which includes a user area of a memory cell array; a buffer area configured to temporarily store compressed data to be written into the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written into the user area. The compressed data management logic manages compressed data to be written into the user area by an ECC block unit rather than by a page-size unit.

Abstract: A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

Abstract: A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.

Abstract: A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.

Abstract: Provided is a memory system that includes at least one nonvolatile memory device, a plurality of power lines and a plurality of power domains. The power lines receive a power source voltage. The power domains are respectively connected to the power lines. A reset signal is generated by using voltages which are detected from the power lines. The memory system and a reset method thereof detect the voltages of all power lines to generate a reset signal, and thus enhance reliability of data when a power is shut off.

Abstract: The booting method of a computing system includes determining whether boot data of an operating system is pinned to a main memory, reading boot data from a storage device to pin the read boot data to the main memory when relocation of the pinned boot data is required, and performing a booting operation using the pinned boot data.

Abstract: Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

Abstract: A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.

Abstract: A data transferring method of a storage device is provided. The method may include transferring a first data to a first outbound area, transferring the first data sent to the first outbound area to a first area of a main memory corresponding to a first address programmed by an address translation unit, transferring a second data to a second outbound area in response to an indication that the address translation unit is to be reprogrammed, and transferring the second data sent to the second outbound area to the first outbound area.

Abstract: A memory controller and an operating method of a memory controller are provided. The operating method includes detecting that a bus of an external host connected with the memory controller enters a first power saving mode; entering a second power saving mode of the memory controller according to a result of the detecting; detecting a wake-up process of the bus of the external host; and waking up the memory controller while the bus of the external host executes the wake-up process. The waking up of the memory controller is ended before the wake-up process of the bus of the external host is completed.

Abstract: A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.

Abstract: A memory controller and an operating method of a memory controller are provided. The operating method includes receiving a command issue from the external host; fetching a command corresponding to the command issue from a memory of the external host in response to the command issue; and controlling the external memory to perform the fetched command. The command is fetched immediately after the command issue is received independently from an execution of a previously fetched command. The memory controller includes a first interface which communicates with a host; and a second interface which communicates with the first interface and with an external memory and is recognized as storage by the host.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.