Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A storage device which includes a user area of a memory cell array; a buffer area configured to temporarily store compressed data to be written into the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written into the user area. The compressed data management logic manages compressed data to be written into the user area by an ECC block unit rather than by a page-size unit.

Abstract: A storage device includes storage media and a controller. The controller includes a de-duplication table that manages hash information for data stored in the storage media, and compares hash information for received write-requested data with hash information managed by the de-duplication table to determine whether the write-requested data is duplicate data.

Abstract: Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation.

Abstract: Provided are a storage device and a user device used by connecting to the user device. The storage device may include a nonvolatile memory and a control unit configured to control the nonvolatile memory. When write data is received from the host, the control unit outputs a first response signal including information indicating whether the write data is successfully received. When the write data is stored in the nonvolatile memory, the control unit outputs a second response signal including on whether the write data is successfully stored in the nonvolatile memory. Since the storage device does not require a program backup memory, it may be implemented in a small area.

Abstract: Provided is a memory system that includes at least one nonvolatile memory device, a plurality of power lines and a plurality of power domains. The power lines receive a power source voltage. The power domains are respectively connected to the power lines. A reset signal is generated by using voltages which are detected from the power lines. The memory system and a reset method thereof detect the voltages of all power lines to generate a reset signal, and thus enhance reliability of data when a power is shut off.

Abstract: A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage.

Abstract: An auxiliary power device includes an auxiliary power source having first and second charging cells connected in series, a cell balance circuit configured to sense a charging voltage between the first and second charging cells, generate a balance voltage based on the sensed charging voltage, and applies the generated balance voltage between the first and second charging cells, and a microprocessor configured to diagnose the first and second charging cells based on the sensed charging cells and control the cell balance circuit.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

Abstract: A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device.

Abstract: The booting method of a computing system includes determining whether boot data of an operating system is pinned to a main memory, reading boot data from a storage device to pin the read boot data to the main memory when relocation of the pinned boot data is required, and performing a booting operation using the pinned boot data.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.