Patents by Inventor Holger Hubner
Holger Hubner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9301396Abstract: A connecting element can be used for a multi-chip module. The connecting element is provided for establishing an electrical connection between two elements and has a carrier and a first electrically conductive connecting structure on a first main surface of the carrier. The first connecting structure is designed in such a way that the first connecting structure connects the first and second elements to each other. A multi-chip module can have such a connecting element and two elements, wherein the two elements are electrically connected to each other in a wireless manner by the connecting element.Type: GrantFiled: August 3, 2012Date of Patent: March 29, 2016Assignee: OSRAM GmbHInventors: Holger Hübner, Björn Hoxhold, Axel Kaltenbacher
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Publication number: 20140291003Abstract: A connecting element can be used for a multi-chip module. The connecting element is provided for establishing an electrical connection between two elements and has a carrier and a first electrically conductive connecting structure on a first main surface of the carrier. The first connecting structure is designed in such a way that the first connecting structure connects the first and second elements to each other. A multi-chip module can have such a connecting element and two elements, wherein the two elements are electrically connected to each other in a wireless manner by the connecting element.Type: ApplicationFiled: August 3, 2012Publication date: October 2, 2014Applicant: OSRAM GMBHInventors: Holger Hübner, Björn Hoxhold, Axel Kaltenbacher
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Patent number: 7436072Abstract: A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first chip and on the second chip there is in each case a connecting element, the connecting element on the first chip forming with the connecting element on the second chip a mechanical connection between the two chips. The connecting element and the functional layer are made of the same material. At least in the case of the first chip or in the case of the second chip, the connecting element is in direct contact with the functional layer.Type: GrantFiled: February 8, 2006Date of Patent: October 14, 2008Assignee: Infineon Technologies AGInventors: Holger Hubner, Berndt Gammel
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Patent number: 7389903Abstract: A device for soldering contacts on semiconductor chips. A chip is held on a chip mount by a chuck and is heated from a side facing away from the wafer by means of a radiation source, so that a solder applied to a side facing the wafer is melted. A flushing device, having a plate with a window, a gas channel, and a gas outlet opening for a forming gas, is arranged at the window, is fitted parallel to the wafer. The chip is moved vertically in relation to the wafer, pressed onto the wafer through the window, and soldered on by means of isothermal solidification.Type: GrantFiled: March 29, 2004Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventors: Robert Bergmann, Holger Hubner
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Patent number: 7335582Abstract: Semiconductor component, having a first chip arranged on a second chip, in which the first and second chips in each case have, on one of their main areas, first and second metalizations, respectively, which face one another. First regions of the metalizations are provided for the production of an electrical connection between the first and second chips. Second regions of the metalization are provided as an additional electrical functional plane outside the first and second chips.Type: GrantFiled: October 27, 2004Date of Patent: February 26, 2008Assignee: Infineon Technologies AGInventor: Holger Hubner
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Publication number: 20070205253Abstract: A method for connecting at least two metal layers by means of a diffusion soldering process, wherein each of the metal layers that is to be connected is plated with a respective solder layer prior to the diffusion soldering process.Type: ApplicationFiled: March 6, 2006Publication date: September 6, 2007Applicant: Infineon Technologies AGInventor: Holger Hubner
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Patent number: 7253530Abstract: A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact with the interconnects applied previously.Type: GrantFiled: September 26, 2005Date of Patent: August 7, 2007Assignee: Infineon Technologies AGInventor: Holger Hubner
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Patent number: 7229851Abstract: A the semiconductor chip stack in which an intermediate space between semiconductor chips is filled at least along one edge of the upper face of a top chip by a spacer composed of a polymer which can be structured photographically, of photoresist, of an encapsulation compound or an adhesive, and is sealed from the outside. During the passivating process, the connecting contact pads are kept free of the material of this spacer for bonding wires or other external connections on the upper face of the bottom chip.Type: GrantFiled: July 11, 2005Date of Patent: June 12, 2007Assignee: Infineon Technologies AGInventor: Holger Hubner
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Publication number: 20060279002Abstract: A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first chip and on the second chip there is in each case a connecting element, the connecting element on the first chip forming with the connecting element on the second chip a mechanical connection between the two chips. The connecting element and the functional layer are made of the same material. At least in the case of the first chip or in the case of the second chip, the connecting element is in direct contact with the functional layer.Type: ApplicationFiled: February 8, 2006Publication date: December 14, 2006Applicant: Infineon Technologies AGInventors: Holger Hubner, Berndt Gammel
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Publication number: 20060055051Abstract: A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact with the interconnects applied previously.Type: ApplicationFiled: September 26, 2005Publication date: March 16, 2006Applicant: Infineon Technologies AGInventor: Holger Hubner
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Publication number: 20060001177Abstract: A the semiconductor chip stack in which an intermediate space between semiconductor chips is filled at least along one edge of the upper face of a top chip by a spacer composed of a polymer which can be structured photographically, of photoresist, of an encapsulation compound or an adhesive, and is sealed from the outside. During the passivating process, the connecting contact pads are kept free of the material of this spacer for bonding wires or other external connections on the upper face of the bottom chip.Type: ApplicationFiled: July 11, 2005Publication date: January 5, 2006Applicant: Infineon Technologies AGInventor: Holger Hubner
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Patent number: 6930383Abstract: The invention relates to an electronic component including a housing and a first substrate having at least one integrated circuit, a multiplicity of contact surfaces arranged in an arbitrary distribution on the surface of the first substrate. A second substrate forms a housing and is mechanically joined to the surface of the first substrate in a surface-to-surface contact, via an insulating joining layer. The second substrate has contact connection surfaces that are surface-to-surface connected to the contact surfaces of the first substrate in an electrically conductive manner. The second substrate has symmetrically arranged external contact surfaces that are conductively connected to the contact connection surfaces via through-contacts in the second substrate.Type: GrantFiled: December 16, 2002Date of Patent: August 16, 2005Assignee: Infineon Technologies AGInventors: Hans-Jürgen Hacke, Holger Hübner, Axel Königer, Max-Gerhard Seitz, Rainer Tilgner
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Patent number: 6915945Abstract: For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining temperature is chosen in such a way that the substrate, with a pressure being exerted on the electrical component, experiences a plastic deformation, with the result that the electrical component is pressed together with the conductor structure into the substrate in a positively locking manner. In order to produce the connection between the component and the substrate, use is preferably made of a thin diffusion solder layer which can be processed at temperatures lying below the melting point of the substrate.Type: GrantFiled: November 21, 2003Date of Patent: July 12, 2005Assignee: Infineon Technologies AGInventor: Holger Hübner
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Patent number: 6906370Abstract: A semiconductor component having a material-reinforced contact area formed of a metal layer is disclosed. The contact area is jointly formed by a second metal area of a first metal layer and a fourth metal area of a second metal layer which is to be contacted. A thickness of the contact area material is at least twice that of a single metal layer and thereby prevents penetrative etching when a hole is created for contacting the metal layer.Type: GrantFiled: October 10, 2000Date of Patent: June 14, 2005Assignee: Infineon Technologies AGInventors: Holger Hübner, Thomas Röhr
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Publication number: 20050121801Abstract: Semiconductor component, having a first chip arranged on a second chip, in which the first and second chips in each case have, on one of their main areas, first and second metalizations, respectively, which face one another. First regions of the metalizations are provided for the production of an electrical connection between the first and second chips. Second regions of the metalization are provided as an additional electrical functional plane outside the first and second chips.Type: ApplicationFiled: October 27, 2004Publication date: June 9, 2005Applicant: Infineon Technologies AGInventor: Holger Hubner
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Patent number: 6872464Abstract: A soldering agent for use in diffusion soldering processes contains, in a soldering paste, a mixture of at least partially metallic grains of a high-melting metal and a solder metal. In a diffusion soldering process, the solder metal reacts completely with the high-melting metal and metals belonging to parts that are to be joined to one another by the soldering process, to form an intermetallic phase.Type: GrantFiled: March 7, 2003Date of Patent: March 29, 2005Assignee: Infineon Technologies AGInventors: Holger Hübner, Vaidyanathan Kripesh
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Publication number: 20040240865Abstract: A device for soldering contacts on semiconductor chips. A chip is held on a chip mount by a chuck and is heated from a side facing away from the wafer by means of a radiation source, so that a solder applied to a side facing the wafer is melted. A flushing device, having a plate with a window, a gas channel, and a gas outlet opening for a forming gas, is arranged at the window, is fitted parallel to the wafer. The chip is moved vertically in relation to the wafer, pressed onto the wafer through the window, and soldered on by means of isothermal solidification.Type: ApplicationFiled: March 29, 2004Publication date: December 2, 2004Applicant: Infineon Technologies AGInventors: Robert Bergmann, Holger Hubner
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Publication number: 20040099366Abstract: For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining temperature is chosen in such a way that the substrate, with a pressure being exerted on the electrical component, experiences a plastic deformation, with the result that the electrical component is pressed together with the conductor structure into the substrate in a positively locking manner. In order to produce the connection between the component and the substrate, use is preferably made of a thin diffusion solder layer which can be processed at temperatures lying below the melting point of the substrate.Type: ApplicationFiled: November 21, 2003Publication date: May 27, 2004Inventor: Holger Hubner
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Patent number: 6709949Abstract: In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is mechanically and electrically connected thereto. To that end, in the second, thinned semiconductor substrate, continuous contact holes are formed proceeding from a substrate rear side as far as a first metal wiring plane on a substrate front side. In order to align the contact holes with the structures arranged on the front side, a structure is arranged on the front side of the substrate, which can be used as an alignment mark on the front side. The structure is overgrown with a useful layer and uncovered proceeding from the rear side of the substrate, so that the structure can also be used as an alignment mark from the rear side. This avoids an alignment error between the structures arranged on the front side and the rear side.Type: GrantFiled: October 21, 2002Date of Patent: March 23, 2004Assignee: Infineon Technologies AGInventor: Holger Hübner
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Publication number: 20040025976Abstract: A soldering agent for use in diffusion soldering processes contains, in a soldering paste, a mixture of at least partially metallic grains of a high-melting metal and a solder metal. In a diffusion soldering process, the solder metal reacts completely with the high-melting metal and metals belonging to parts that are to be joined to one another by the soldering process, to form an intermetallic phase.Type: ApplicationFiled: March 7, 2003Publication date: February 12, 2004Inventors: Holger Hubner, Vaidyanathan Kripesh