Patents by Inventor Holger Torwesten
Holger Torwesten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10964642Abstract: A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.Type: GrantFiled: January 23, 2018Date of Patent: March 30, 2021Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Andre Arens, Holger Torwesten
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Patent number: 10192849Abstract: A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules.Type: GrantFiled: February 10, 2014Date of Patent: January 29, 2019Assignee: Infineon Technologies AGInventors: Petteri Palm, Alexander Heinrich, Holger Torwesten, Tobias Simbeck
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Publication number: 20180211917Abstract: A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.Type: ApplicationFiled: January 23, 2018Publication date: July 26, 2018Applicant: Infineon Technologies AGInventors: Juergen Hoegerl, Andre Arens, Holger Torwesten
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Patent number: 9553051Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.Type: GrantFiled: February 2, 2015Date of Patent: January 24, 2017Assignee: Infineon Technologies Austria AGInventors: Petteri Palm, Holger Torwesten, Manfred Schindler, Boris Plikat
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Publication number: 20160225717Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.Type: ApplicationFiled: February 2, 2015Publication date: August 4, 2016Inventors: Petteri Palm, Holger Torwesten, Manfred Schindler, Boris Plikat
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Patent number: 9245868Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.Type: GrantFiled: June 27, 2012Date of Patent: January 26, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Holger Torwesten, Manfred Mengel
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Patent number: 9214442Abstract: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.Type: GrantFiled: March 19, 2007Date of Patent: December 15, 2015Assignee: Infineon Technologies AGInventors: Karsten Guth, Holger Torwesten
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Publication number: 20150228616Abstract: A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: Infineon Technologies AGInventors: Petteri Palm, Alexander Heinrich, Holger Torwesten, Tobias Simbeck
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Patent number: 8945990Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.Type: GrantFiled: April 24, 2012Date of Patent: February 3, 2015Assignee: Infineon Technologies AGInventors: Holger Torwesten, Manfred Mengel, Stefan Schmid, Soon Lock Goh, Swee Kah Lee
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Patent number: 8709876Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.Type: GrantFiled: September 11, 2012Date of Patent: April 29, 2014Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Holger Torwesten
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Publication number: 20140001634Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Holger Torwesten, Manfred Mengel
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Publication number: 20130277813Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Holger Torwesten, Manfred Mengel, Stefan Schmid, Soon Lock Goh, Swee Kah Lee
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Patent number: 8367514Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: January 29, 2010Date of Patent: February 5, 2013Assignee: Infineon Technologies AGInventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Publication number: 20130005144Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Manfred Schneegans, Holger Torwesten
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Patent number: 8264072Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.Type: GrantFiled: October 22, 2007Date of Patent: September 11, 2012Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Holger Torwesten
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Patent number: 8263491Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.Type: GrantFiled: October 19, 2007Date of Patent: September 11, 2012Assignee: Infineon Technologies AGInventors: Florian Binder, Stephan Dertinger, Barbara Hasler, Alfred Martin, Grit Sommer, Holger Torwesten
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Patent number: 7755190Abstract: An electronic device and the production thereof is disclosed. One embodiment includes an integrated component having a layer containing a nickel-palladium alloy.Type: GrantFiled: August 7, 2007Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Holger Torwesten
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Publication number: 20100129977Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: ApplicationFiled: January 29, 2010Publication date: May 27, 2010Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Patent number: 7692266Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: March 3, 2006Date of Patent: April 6, 2010Assignee: Infineon Technologies A.G.Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
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Publication number: 20090102032Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.Type: ApplicationFiled: October 22, 2007Publication date: April 23, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Manfred Schneegans, Holger Torwesten