Abstract: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

Abstract: An electronic device and the production thereof is disclosed. One embodiment includes an integrated component having a layer containing a nickel-palladium alloy.

Abstract: A method for electroplating is provided in which a copper layer is patterned using a resist. A barrier layer lies below the copper layer and is used to supply the electroplating current in regions without the copper layer. The method makes it possible to produce high-quality soldering bumps.

Abstract: One aspect of the invention relates to an interconnecting element between a semiconductor chip of a semiconductor wafer and a circuit support and to a method for producing and using the interconnecting element. Such interconnecting elements are arranged between contact areas of a semiconductor chip of a semiconductor wafer and contact terminal areas of a circuit support. The contact areas on the semiconductor chip or the semiconductor wafer, respectively, are arranged in depressions of a top of an insulating cover layer and are freely accessible. The interconnecting elements have a mushroom shape with a mushroom cap in a first metal area. On the mushroom cap of the first metal area, a second metal area is arranged which has high-melting intermetallic phases of metals of a solder material and the metal of the contact terminal areas of the circuit support.

Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.