Patents by Inventor Homare Sato

Homare Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070246440
    Abstract: A semiconductor memory device is provided in which a phase-change layer can be formed stably and electric current required to cause the phase change of the phase-change layer can be reduced. An edge portion of the phase-change layer is formed above a lower electrode. The edge portion is formed to assume a tapered shape in cross section such that the thickness of the phase-change layer varies above the contact area between the lower electrode and the phase-change layer. The tapered portion is filled with an oxide film. According to this configuration, the region in which the phase-change occurs can be restricted, and hence the phase-change layer can be heated efficiently, resulting in reduction of electric current required for heating.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 25, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Homare Sato
  • Publication number: 20070120128
    Abstract: A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly connected to a source line, and the drain regions are each connected to a lower electrode of a different memory element. According to the present invention, it is possible to assign three cell transistors connected in parallel to one memory element, so that an effective gate width is further increased.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 31, 2007
    Inventors: Homare Sato, Kiyoshi Nakai
  • Publication number: 20070114510
    Abstract: A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 24, 2007
    Inventors: Homare Sato, Kiyoshi Nakai