Patents by Inventor Home-Been Cheng

Home-Been Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130256843
    Abstract: A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 3, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsin-Yu CHEN, Home-Been Cheng, Ching-Li Yang
  • Patent number: 8518823
    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 27, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
  • Publication number: 20130161796
    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng