Abstract: Semiconductor chips with curable out of specification measured values of an anneal-activated parameter are identified at a test step. A plurality of anneal plans are generated to include at least one of the identified semiconductor chips. A net yield improvement is calculated for each anneal plan. Each anneal plan includes the paths of a laser beam across the wafer to be irradiated, and optionally includes an azimuthal angle of the wafer as a function of time. The net yield improvement is the difference between an estimated yield improvement from selected target semiconductor chips for irradiation and an estimated yield loss due to collateral irradiation of functional semiconductor chips for each anneal plan. After simulating the net yield improvements for all the anneal plans, the anneal plan providing the greatest net yield improvement can be selected and utilized.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.

Abstract: In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions.

Abstract: Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer.

Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

Abstract: A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Abstract: In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of substrate. The dummy gate is removed and the height of the gate channel is reduced to substantially near that of a top surface of one or more FINs. A layer of high-k material is deposited into the gate channel. A layer of first metal is then deposited that fills the gate channel and covers, at least in part, the layer of high-k material. Excess material is removed from the layers of high-k material and first metal to create a surface. A layer of second metal is selectively deposited onto the surface to form a continued gate conductor.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.

Abstract: The system provides secure controlled access to multiple Bluetooth devices issued to users. For example an officer may be issued a weapon. To enable monitoring of weapon status, a Bluetooth sensor may be fitted to a holster and the Officer issued with a Bluetooth enabled mobile phone. In order to establish a secure Bluetooth connection between the devices, sensor contains a restored link key and the mobile phone stores a partial link key. The supervisor enters their username and password, and a secret key into the phone which is then used with the partial link key to generate a copy of the link key stored in the first device, so that a secure connection can be established with the first device. The officer enters their username and password into the sensor, and once the secure connection is established it is sent over the secure connection to the mobile phone which then sends both user names and passwords to a verification authority.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.

Abstract: In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions.

Abstract: In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions.