Abstract: Devices, systems, and methods for palette mode coding are described. An exemplary method for video processing includes performing a conversion between a block of a video and a bitstream representation of the video. The bitstream representation is processed according to a format rule that specifies a first indication of usage of a palette mode and a second indication of usage of an intra block copy (IBC) mode are signaled dependent of each other.

Abstract: In an exemplary aspect, a method for visual media processing includes identifying a boundary at a vertical edge and/or a horizontal edge of two video blocks; calculating a boundary strength of a filter based on at least one of the two video blocks crossing a vertical edge or a horizontal edge is coded using a combined intra-inter prediction (CIIP) mode; deciding whether to turn on or off the filter; selecting a strength of the filter in case the filter is turned on; and performing, based on the selecting, a deblocking filter (DB) process to the video blocks.

Abstract: A fusion method of satellite-based and ground-based lightning data includes S1, selecting valid data in the satellite-based and ground-based lightning data; S2, determining a time threshold for fusing the satellite-based and ground-based lightning data; S3, determining a spatial threshold for fusing the satellite-based lightning data and the ground-based lightning data; and S4, constructing a data fusion scheme to obtain a fused all lightning data set.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: Video processing methods, systems and appratrus are described. One example method includes performing a conversion between a video block of a video and a bitstream of the video using a palette mode in which samples of the video block are represented using a palette of representive color values. A size of the palette of the video block is determined based on whether a local dual tree is applied for the conversion.

Abstract: A weeding device for crops having a seedling avoidance function includes a rack connected to a weeding machine. A hydraulic pump and two hydraulic cylinders are mounted to the rack. Bottom ends of each of the two hydraulic cylinders are provided with a vertically arranged support rod. An inter-row weeder is mounted to a bottom end of each of the two support rods. A slider configured to reciprocate in a horizontal direction is positioned on two slide rails that are mounted to the rack. An inter-plant weeder is mounted to a bottom side of the slider. A plurality of weeder blades are arranged side by side on the inter-plant weeder. At the weeding position, an arrangement direction of weeder blades is perpendicular to an advancing direction, and at the weed avoidance position, the arrangement direction of the weeder blades is parallel to the advancing direction, thereby avoiding crops.

Abstract: Devices, systems and methods for palette mode coding are described. An exemplary method for video processing includes performing a conversion between a block of a video and a bitstream representation of the video. The bitstream representation is processed according to a format rule that specifies a first indication of usage of a palette mode and a second indication of usage of an intra block copy (IBC) mode are signaled dependent of each other.

Abstract: Video processing methods, systems and apparatus are described. One example method includes performing a conversion between a video block of a video and a bitstream of the video using a palette mode in which samples of the video block are represented using a palette of representative color values. A size of the palette of the video block is determined based on whether a local dual tree is applied for the conversion.

Abstract: Extensions of intra coding modes in video coding are described. One example is a method for video processing, comprising: generating, for a conversion between a current video block of a video and a bitstream representation of a video, a set of extended intra prediction modes (IPMs) associated with the current video block by revising a set of existing IPMs to include at least one new coding method, wherein the new coding method is different from coding methods in the existing IPMs and is to be treated as IPM; and performing the conversion based on the set of extended IPMs.

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

Abstract: A memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.

Abstract: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate and a stack structure in an insulating structure on the substrate. The stack structure includes alternating a plurality of conductor layers and a plurality of insulating layers. The 3D memory device further includes a source structure extending vertically through the alternating stack structure. The source structure includes at least one staggered portion along a respective sidewall. The 3D memory device further includes a channel structure and a support pillar each extending vertically through the alternating stack structure and a plurality of contact structures extending vertically through the insulating structure.

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A structure extending vertically through a memory stack including interleaved conductive layers and dielectric layers is formed above a substrate. A first dielectric layer is formed on the memory stack. An etch stop layer is formed on the first dielectric layer. A first contact is formed through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure. A second dielectric layer is formed on the etch stop layer. A second contact is formed through the second dielectric layer and in contact with at least an upper end of the first contact.

Abstract: A method for forming a 3D memory device is disclosed. A gate electrode having an inverted “T” shape is formed above a substrate. A continuous blocking layer is formed on the gate electrode. A continuous charge trapping layer is formed on the blocking layer. A first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically. The second part of the charge trapping layer extending vertically is removed to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally. A continuous tunneling layer is formed on the discrete charge trapping layers. A continuous channel layer is formed on the tunneling layer.