Patents by Inventor Hong Bok We

Hong Bok We has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Split conductive pad for device terminal
    Patent number: 10879158
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, Kuiwon Kang, Zhijie Wang
  • DOUBLE SIDED EMBEDDED TRACE SUBSTRATE
    Publication number: 20200388573
    Abstract: Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 10, 2020
    Inventors: Kuiwon KANG, Zhijie WANG, Hong Bok WE
  • SPLIT CONDUCTIVE PAD FOR DEVICE TERMINAL
    Publication number: 20200381344
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: Aniket PATIL, Hong Bok WE, Kuiwon KANG, Zhijie WANG
  • PASSIVE DEVICE EMBEDDED IN A FAN-OUT PACKAGE-ON-PACKAGE ASSEMBLY
    Publication number: 20200381405
    Abstract: Certain aspects of the present disclosure generally relate to a chip assembly having an embedded passive device in a bottom package of a package-on-package (PoP) assembly. An example chip assembly generally includes a first package and a second package disposed above and coupled to the first package. The first package may include a redistribution layer, an integrated circuit die disposed above and coupled to the redistribution layer, and at least one reactive component disposed above the redistribution layer and coupled to the redistribution layer and the second package.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Aniket PATIL, Hong Bok WE, Bernie YANG
  • ENHANCED ANTENNA MODULE WITH SHIELD LAYER
    Publication number: 20200365983
    Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 19, 2020
    Inventors: Suhyung HWANG, Chin-Kwan Kim, Hong Bok We, Jaehyun Yeon
  • ASYMMETRIC ANTENNA STRUCTURE
    Publication number: 20200212545
    Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Suhyung HWANG
  • SUBSTRATE COMPRISING RECESSED INTERCONNECTS AND A SURFACE MOUNTED PASSIVE COMPONENT
    Publication number: 20200135839
    Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Kuiwon KANG, Chin-Kwan KIM, Hong Bok WE, Jaehyun YEON
  • SPILT PAD FOR PACKAGE ROUTING AND ELECTRICAL PERFORMANCE IMPROVEMENT
    Publication number: 20200111758
    Abstract: In conventional panel level packaging, the BGA pad itself can occupy more space on the final connection layer leaving less space to route traces and vias. To address this and other issues, connection pads such as the BGA pad can be split to allow for more efficient routing on the final connection layer.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Aniket PATIL, Hong Bok WE, Brigham NAVAJA, Moshiul HAQUE
  • INTEGRATED CIRCUIT CAVITY FORMATION WITH MULTIPLE INTERCONNECTION PADS
    Publication number: 20200091062
    Abstract: Certain aspects of the present disclosure provide techniques for forming a cavity with various conductive pad interconnections for receiving an electronic component in an integrated circuit. One example method of fabricating an integrated circuit generally includes forming a conductive metal above a first substrate layer, forming a barrier metal above the conductive metal, disposing at least one second substrate layer above the barrier metal, forming a cavity in the at least one second substrate layer by using a laser to expose the barrier metal and the conductive metal in the cavity, and etching the conductive metal in the form of a conductive pad pattern for coupling the conductive metal to an electronic component.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Jaehyun YEON, Hong Bok WE, Chin-Kwan KIM, Kuiwon KANG
  • INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME
    Publication number: 20200066964
    Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: Jon Gregory ADAY, Hong Bok WE, Steve Joseph BEZUK, Nicholas Ian BUCHAN
  • Interface substrate and method of making the same
    Patent number: 10516092
    Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Gregory Aday, Hong Bok We, Steve Joseph Bezuk, Nicholas Ian Buchan
  • INTEGRATED CIRCUIT CHIP PACKAGE HAVING REDUCED CONTACT PAD SIZE
    Publication number: 20190371652
    Abstract: An interconnect comprises a dielectric, a via formed in the substrate having a first diameter and a second diameter, and a contact pad for aligning the via on the substrate along the second diameter, wherein the contact pad has a width smaller than the second diameter. The contact pad may be line-shaped. The second diameter is approximately 2×-10× bigger than the contact pad width. The contact pad width is approximately 2-15 microns, and the first diameter is approximately 10-60 microns. The substrate may be used for routing input/output signals and design. The via may be performed using photolithography, laser ablation, and/or plasma etching.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Kuiwon KANG
  • Air cavity mold
    Patent number: 10490472
    Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jie Fu, Hong Bok We, Manuel Aldrete
  • TAPERED CORNER PACKAGE FOR EMI SHIELD
    Publication number: 20190341352
    Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Manuel ALDRETE, David Fraser RAE
  • Thermal and electromagnetic interference shielding for die embedded in package substrate
    Patent number: 10410971
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: David Fraser Rae, Hong Bok We, Christopher Healy, Chin-Kwan Kim
  • Array type inductor
    Patent number: 10403707
    Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Chin-Kwan Kim, Joonsuk Park
  • AIR CAVITY MOLD
    Publication number: 20190067141
    Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Jie FU, Hong Bok WE, Manuel ALDRETE
  • THERMAL AND ELECTROMAGNETIC INTERFERENCE SHIELDING FOR DIE EMBEDDED IN PACKAGE SUBSTRATE
    Publication number: 20190067205
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: David Fraser RAE, Hong Bok WE, Christopher HEALY, Chin-Kwan KIM
  • INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE
    Publication number: 20190057880
    Abstract: Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Inventors: Young Kyu SONG, Kyu-Pyung HWANG, Hong Bok WE
  • Integrated circuit package comprising surface capacitor and ground plane
    Patent number: 10181410
    Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Hong Bok We