Patents by Inventor Hong Bok We

Hong Bok We has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157823
    Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dong Wook Kim, Hong Bok We, Jae Sik Lee, Shiqun Gu
  • Publication number: 20180350630
    Abstract: Exemplary packages according to some aspects of the disclosure may include a symmetric structure with a thick core for embedded trace substrates. The packages may include an embedded third dielectric layer for preventing bump shorts or trace peel off between fine bump areas with a solder resist trench. This may allow fine bump pitches with escape lines (traces) on flip chip bump array (FCBGA) applications, for example.
    Type: Application
    Filed: November 15, 2017
    Publication date: December 6, 2018
    Inventors: Kuiwon KANG, Marcus HSU, Hong Bok WE
  • Publication number: 20180286562
    Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Hong Bok WE, Chin-Kwan KIM, Joonsuk PARK
  • Patent number: 10079097
    Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: September 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, Hong Bok We, Kyu-Pyung Hwang
  • Patent number: 10049977
    Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Jae Sik Lee, Kyu-Pyung Hwang, Young Kyu Song
  • Patent number: 9881859
    Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Jae Sik Lee, Shiqun Gu, Ratibor Radojcic
  • Patent number: 9875997
    Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Kyu-Pyung Hwang, Young Kyu Song
  • Publication number: 20170323926
    Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.
    Type: Application
    Filed: September 2, 2016
    Publication date: November 9, 2017
    Inventors: Jon Gregory ADAY, Hong Bok WE, Steve Joseph BEZUK, Nicholas Ian BUCHAN
  • Patent number: 9799628
    Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Dong Wook Kim, Hong Bok We, Jae Sik Lee, Shiqun Gu
  • Publication number: 20170243845
    Abstract: A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects couple to pads on an encapsulated die. The interconnects have a pad-facing surface that couples to a corresponding pad through a seed layer. The seed layer does not cover the sidewalls of the interconnects.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Jae Sik Lee, Hong Bok We, Dong Wook Kim
  • Patent number: 9679855
    Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jae Sik Lee, Hong Bok We, Dong Wook Kim, Jon Aday
  • Patent number: 9659850
    Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Kyu-Pyung Hwang, Young Kyu Song, Dong Wook Kim
  • Publication number: 20170125332
    Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.
    Type: Application
    Filed: February 27, 2015
    Publication date: May 4, 2017
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Hong Bok We
  • Patent number: 9642259
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 2, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Omar James Bchir, Dong Wook Kim, Hong Bok We
  • Patent number: 9633977
    Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Shiqun Gu, Urmi Ray, Ratibor Radojcic
  • Patent number: 9633950
    Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 25, 2017
    Inventors: Hong Bok We, Jae Sik Lee, Dong Wook Kim
  • Patent number: 9628052
    Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Kyu-Pyung Hwang, Young Kyu Song
  • Patent number: 9613942
    Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jae Sik Lee, Kyu-Pyung Hwang, Hong Bok We
  • Publication number: 20170084594
    Abstract: A die can be mounted on an already made pattern. Thereafter, substrate and other metal layers can be provided so as to embed the die in the substrate. This avoids the need to form a cavity in the substrate for die placement prevalent in conventional die embedding processes. As a result, die embedding process can be simplified. Also, die misalignment can be reduced or eliminated.
    Type: Application
    Filed: September 20, 2015
    Publication date: March 23, 2017
    Inventors: Jongchil NA, Hong Bok WE, Ruey Kae ZANG
  • Patent number: 9595496
    Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: March 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jae Sik Lee, Hong Bok We, Dong Wook Kim, Shiqun Gu