Abstract: A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.

Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.

Abstract: The present disclosure provides a shielding apparatus for a lower end of an injection needle and an injection device, and relates to the technical field of injection instruments. By using the shielding apparatus for a lower end of an injection needle in the present disclosure, in the process of mounting a needle holder on an insulin pen, and when the injection needle is completely removed from the insulin pen, the limit block also moves downwardly to abut against a bottom wall of the moving groove, and the shielding cylinder completely covers the lower end of the injection needle, so as to avoid a situation that a user accidentally touches the lower end of an injection needle to be injured, thereby avoiding the safety risk when the lower end of the injection needle is removed.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.

Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.

Abstract: Aspects presented herein may enable a first UE to utilize inference results provided by at least a second UE to improve its inference accuracy. In one aspect, a first UE establishes an ML inference result sharing session with one or more second UEs for at least one ML inference task. The first UE receives a first set of ML inference results associated with the at least one ML inference task, where the first set of ML inference results is received from the one or more second UEs during the ML inference result sharing session. The first UE estimates an aggregated ML inference result based on at least one of the first set of ML inference results or a second set of ML inference results, where the second set of ML inference results is configured by the first UE for the at least one ML inference task.

Abstract: A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.

Abstract: A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.

Abstract: The present disclosure provides a safe puncture needle, and relates to the technical field of medical devices, which comprises a needle holder, a base and a needle tubing, wherein the needle tubing comprises a needle tubing body and a needle tubing tip having a bent structure, the base comprises a base body and a guide block, the base body is provided with a second inner space, the base body is provided with a first through-hole and a second through-hole communicating with the second inner space, the guide block is provided with a third through-hole, the needle tubing body passes through the first through-hole and the third through-hole and is slidably connected to the guide block, and the needle tubing tip retracts from the second through-hole.

Abstract: A chip package having four sides provided with electromagnetic interference (EMI) shielding layers correspondingly and a method of manufacturing the same are provided. The four EMI shielding layers are made of metals, located on four lateral sides of the chip package, and completely covering four lateral sides of a substrate and four lateral sides of an insulating layer to prevent at least one first circuit layer, at least one second circuit layer, and at least one chip from electromagnetic interference. Moreover, the EMI shielding layers help to improve heat dissipation efficiency of the first circuit layer, the second circuit layer, and the chip.

Abstract: A chip package with an electromagnetic interference shielding layer and a method of manufacturing the same are provided. The chip package includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, a first insulating layer, and at least one electromagnetic interference shielding layer. The electromagnetic interference shielding layer is made of metals and covering a first surface of the first insulating layer completely for preventing the respective first circuit layers, the respective second circuit layers, and the respective chips from external electromagnetic interference (EMI).

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.

Abstract: A chip package unit, a method of manufacturing the same, and package structure formed by stacking the same are provided. At least one first connecting pad, at least one second connecting pad, and at least one third connecting pad of a flexible printed circuit (FPC) board in the chip package unit are electrically connected with one another by circuit of the FPC board. At least one die pad disposed on a front surface of a chip is electrically connected with the first connecting pad first and then electrically connected with the outside by the second connecting pad or the third connecting pad. Thereby the chip of the chip package unit can be electrically connected with the outside by the front surface or a back surface thereof. Therefore, not only production is reduced due to simplified production process and energy saved, volume of the package structure is also reduced.

Abstract: A chip package unit, a method of manufacturing the same, and a package structure formed by stacking the same are provided. The chip package unit is formed by cutting of a wafer separately. The chip package unit includes a chip, a first redistribution layer (RDL), a second RDL, and at least one first circuit layer. The first circuit layer is electrically connected with and disposed between a first conductive circuit and a second conductive circuit. The first circuit layer is located at least one first lateral side of the chip, at least one second lateral side of the first RDL, and at least one third lateral side of the second RDL. The chip can be electrically connected with the outside by the first conductive circuit or the second conductive circuit. Thereby manufacturing process is simplified and manufacturing cost is further reduced.

Abstract: A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.

Abstract: A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.

Abstract: A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 ?m to 20 ?m. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.